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Journal Papers

  1. G. Haidar, J. Zhou, S. Islam, M. Tehranipoor, and F. Farahmandi, “SAFET-HI: Secure Authentication-based Framework for Encrypted Testing in Heterogeneous Integration,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2025.
  2. P. Calzada, Z. Ibnat, T. Rahman, K. Kandula, D. Lu, S. K. Saha, F. Farahmandi, and Mark Tehranipoor, “VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL Generation” ArXiv, https://www.arxiv.org/abs/2507.13369, 2025.
  3. D. Saha, S. Tarek, H. Al Shaikh, K. T. Hasan, P. S. Nalluri, A. Hasan, N. Alam, J. Zhou, S. K. Saha, M. Tehranipoor, and F. Farahmandi, “SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models,” https://arxiv.org/abs/2506.20415, 2025.
  4. U. Das, S. Rahman, A. Kulkarny, M. Tehranipoor, and F. Farahmandi, “PSCMark: Power Side Channel-Based Watermarking for SoC IPs Using Clock Gates,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2025.
  5. H. Al-Sjaikh, S. Saha, S. Kumar, F. Farahmandi, and M. Tehranipoor, “Rethinking System-on-Chip Verification for Security Cross-Layer Interactions,’ IEEE Design & Test of Computers (D&T), 2025.
  6. P. Sarker, U. Das, M. Monjil, J. Zhou, F. Farahmandi, and M. Tehranipoor, “GEM-Water: Generation of EM-based Watermark with Hidden FSM for SoC IPs to Combat Piracy,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.
  7. R. Guo, S. Rahman, J. Zhou, H. Kamali, F. Rahman, F. Farahmandi, and M. Tehranipoor, “EvoLUTe+: Fine-Grained Look-Up-Table-based RTL IP Redaction,” ePrint, 2025.
  8. K. Bepary, T. Zhang, J. Zhuo, F. Rahman, F. Farahmandi, M. Tehranipoor, “Towards Efficiant Gate-Level Electromagnetic Side-Channel Leakage Modeling and Vulnerability Assessment,” Journal of Hardware and Systems Security (HaSS), 2025.
  9. P. P. Sarker, U. Das, N. Varshney, S. Shi. A. Kulkarni, F. Farahmandi, and M. Tehranipoor, “When Everyday Devices Become Weapons: A Closer Look at the Pager and Walkie-talkie Attacks,” arXive, https://arxiv.org/pdf/2501.17405, 2025.
  10. H. Al Shaikh, S. Saha, K. Z. Azar, F. Farahmandi, M. TEHRANIPOOR, and F. Rahman, “Re-Pen: Reinforcement Learning Enforced Penetration Testing for SoC Security,” IEEE Transactions on VLSI (TVLSI), 2025.
  11. K. Bepary, A. Basu, S. Mohammad, R. Hassan, F. Farahmandi, and M. Tehranipoor, “SPY-PMU: Side-Channel Profiling of Your Performance Monitoring Unit to Leak Remote User Activity,” IACR ePrint, https://eprint.iacr.org/2025/014.pdf, 2025.
  12. R. Kibria, F. Farahmandi, and M. Tehranipoor, “A Survey on SoC Security Verification Methods at the Pre-silicon Stage,” IACR ePrint, https://eprint.iacr.org/2024/1280.pdf , 2024.
  13. R. Karri, J. Rajski, Rob Aitken, S. Mitra, and M. Tehranipoor, “VLSI Test and Trust Roundtable,” IEEE Design & Test of Computers (D&T), 2024.
  14. K. Bepary, T. Zhang, F. farahmandi, and M. Tehranipoor, “PreSCAN: A Comprehensive Review of Pre-Silicon Physical Side-Channel Vulnerability Assessment Methodologies,” MDPI Chips, 2024.
  15. D. Saha, S. Tarek, K. Yahyaei, S. K. Saha, J. Xhou, M. Tehranipoor, and F. Farahmandi, “LLM for SoC Security: A Paradigm Shift,” IEEE ACCESS, 2024.
  16. S. Tarek, D. Saha, S. Saha, M. Tehranipoor, and F. Farahmandi, “SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation,” ePrint, https://eprint.iacr.org/2024/983.pdf.
  17. A. Ayalasomayajula, N. Farzana, M. Tehranipoor, and F. Farahmandi, “Automatic Asset Identification for Assertion-based SoC Security Verification,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
  18. M. R. Muttaki, M. H. Rahman, A. Kulkani, M. Tehranipoor, and F. Farahmandi, “FTC: A Universal Framework for Fault-Injection Attack Detection and Prevention,” IEEE Transactions on VLSI (TVLSI), 2024.
  19. A. M. Shuvo, T. Zhang, F. Farahmandi, and M. Tehranipoor, “FLAT: Layout-Aware and Security Property Assisted Timing Fault-Injection Attack Assessment,” IEEE Transactions on VLSI (TVLSI), 2024.
  20. S. U. I. Sami, T. Zhang, A. Mazumder, S. Haque, P. Calzada, K. Z. Azar, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration,” IEEE Access, 2024.
  21. M. M. Hossain, K. Z. Azar, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Fuzzing for Automated SoC Security Verification: Challenges and Solution,” IEEE Design & Test of Computers (D&T), 2024.
  22. T. Zhang, S. Shi, M. H. Rahman, N. Varshney, A. Kulkarni, F. Farahmandi, and M. Tehranipoor, “INSPECT: Investigating Supply Chain and Cyber-Physical Security of Battery Systems,” ePrint, 2024. https://eprint.iacr.org/2024/211.pdf
  23. K. Z. Azar, H. M. Kamali, F. Farahmandi, and M. Tehranipoor, “Improving Bounded Model Checkers Scalability for Circuit De-obfuscation: An Exploration,” IEEE Transactions on Information Forensics & Security (TIFS), 2024.
  24. S. Rajendran, N. Farzana, S. Tarek, H. Kamali, F. Farahmandi, and M. Tehranipoor, “Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities beneath Softwar,” IEEE Transactions on Information Forensics & Security (TIFS), 2024.
  25. N. Farzana, A. Ayalasomayajula, M. Tehranipoor, and F. Farahmandi, “AGILE: Automated Assertion Generation to Detect Information Leakage,” IEEE Transactions on Information Forensics & Security (TIFS), 2024.
  26. T. Zhang, M. Tehranipoor, and F. Farahmandi, “TrustGuard: Standalone FPGA-based Security Monitoring Through Power Side-Channel,” IEEE Transactions on VLSI (TVLSI), 2024.
  27. M. H. Monir, K. Z. Azar, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Fuzzing for Automated SoC Security Verification: Challenges and Solutions,” IEEE Design & Test of Computers (D&T), 2024.
  28. A. Mazumder, T. Zhang, F. farahmandi, M. Tehranipoor, “A Comprehensive Survey on Non-Invasive Fault Injection Attacks,” 2023, ePrint, https://eprint.iacr.org/2023/1769.pdf
  29. D. Saha, S. Tarek, K. Yahyaei, S. Kumar, J. Zhuo, M. Tehranipoor, and F. Farahmandi, “LLM for SoC Security: A Paradigm Shift” 2023, ePrint, https://eprint.iacr.org/2023/1561.pdf
  30. P. Calzada, M. S. Ul Islam, K. Z. Azar, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Heterogeneous Integration Supply Chain Integrity through Blockchain and CHSM,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2023.
  31. M. S. Khan, C. Xi, M. S. Ul Haque, M. Tehranipoor, and N. Asadi, “Exploring Advanced Packaging Technologies for Reverse Engineering a System-in-Package (SiP),” IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), 2023.
  32. M. M. Rahman, S. Tarek, K. Z. Azar, M. Tehranipoor, and F. Farahmandi, “Efficient SoC Security Monitoring: Quality Attributes and Potential Solutions,” IEEE Design & Test of Computers (D&T), 2023.
  33. M. Tao, M. S. Rahman, N. Varshney, M. Tehranipoor, and D. Forte, “iProbe: Internal Shielding Approach for Protecting Against Front-side and Back-side Probing Attacks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.
  34. S. S. Ul Islam, H. M. Kamali. F. Farahmandi, F. Rahman, and M. Tehranipoor, “Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations,” IEEE Design & Test of Computers (D&T), 2023.
  35. R. Kibria, F. Farahmandi, and M. Tehranipoor, “FSMx-Ultra: Finite State Machine Extraction from Gate-Level Netlist for Security Assessment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.
  36. N. Jessurun, O. D. Paradis, J. Harrison, S. Shosh, M. Tehranipoor, D. Woodard, N. Asadi, “FPIC: A Novel Semantic Dataset for Optical PCB Assurance,” ACM Journal of Emerging Technologies in Computing Systems (JETC), 2023.
  37. S. Rahman, R. Gui, H. M. Kamali, F. Rahman, F. Farahmandi, and M. Tehranipoor, “ReTrustFSM: Towards RTL Hardware Obfuscation – A Hybrid FSM Approach,” IEEE Access, 2023.
  38. T. Zhang, F. Rahman, M. Tehranipoor, and F. Farahmandi, “FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain with Blockchain Technology,” IEEE Design & Test of Computers (D&T), 2023.
  39. N. Vashistha, M. L. Rahman, S. Haque, A. Uddin, S. Islam Sami, A. Mazumder, P/ Calzada, F. Farahmandi, N. Asadi, F. Rahman, and M. Tehranipoor, “ToSHI – Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance,” IACR Cryptology ePrint Archive, August 2022, https://eprint.iacr.org/2022/984.pdf
  40. S. Dey, J. Park, N. Pundir, D. Saha, A. mazumdar, D. Mehta, N. Asadi, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Secure Physical Design,” IACR Cryptology ePrint Archive, May 2022, https://eprint.iacr.org/2022/891
  41. D. Mehta, J. True, O. Dizon-Paradis, N. Jessurun, D. Woodard, N. Asadi, and M. Tehranipoor, “FICS PCB X-ray: A Dataset for Automated Printed Circuit Board Inter-Layers Inspection,” IACR Cryptology ePrint Archive, May 2022. https://eprint.iacr.org/2022/924
  42. L. Biswas, L. Lavdas, T. Rahman, M. Tehranipoor, and N. Asadi, “On Backside Probing Techniques and their Emerging Security Threats,” IEEE Design & Test of Computers (D&T), 2022.
  43. M. M. Hossain, N. Vashistha, J. Allen, M. Allen, F. Farahmandi, F. Rahman, and M. Tehranipoor, “Thwarting Counterfeit Electronics by Blockchain,” IEEE Blockchain, 2022.
  44. N. Pundir, J. Park, F. farahmandi, and M. Tehranipoor, “Power Side-Channel Leakage Assessment Framework at Register-Transfer Level,” IEEE Transactions on VLSI (TVLSI), 2022.
  45. J. Park, N. Anandakumar, D. Saha, D. Mehta, N. Pundir, F. Rahman, F. Farahmandi, and M. Tehranipoor, “PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms,” IACR Cryptology ePrint Archive, May 2022, https://eprint.iacr.org/2022/527.pdf
  46. K. Z. Azar, M. M. Hossain, A. Vafaei, H. Al Sheikh, N. Mondol, F. Rahman, M. Tehranipoor, and F. Farahmandi, “Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions,” IACR Cryptology ePrint Archive, March 2022, https://eprint.iacr.org/2022/394.pdf
  47. Y. Bai, A, Stern, J. Park, M. Tehranipoor, and D. Forte, “RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2022.
  48. Y. Bai, J. Park, M. Tehranipoor, and D. Forte, “Real-time Instruction-level Verification of Remote IoT/CPS Devices via Side-Channels,” Springer Discover Internet of Things, 2022.
  49. H. A. Shaikh, M. B. Monjil, S. Chen, F. Farahmandi, N. Asadi, M. Tehranipoor, and F. Rahman, “Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications,” IACR Cryptology ePrint Archive, https://eprint.iacr.org/2022/258.pdf
  50. H. M. Kamali, K. Z. Azar, F. Farahmandi, and M. Tehranipoor, “Advances in Logic Locking: Past, Present, and Prospects,” IACR Cryptology ePrint Archive, https://eprint.iacr.org/2022/260.pdf
  51. N. N. Anandakumar, M. S. Rahman, M. M. M. Rahman, R. Kibria, U. Das, F. Farahmandi, F. Rahman, M. Tehranipoor, “Rethinking watermark: Providing Proof of IP Ownership in Modern SoCs,” IACR Cryptology ePrint Archive, https://eprint.iacr.org/2022/092.pdf
  52. S. Khan, C. Xi, A. Khan, T. Rahman, M. Tehranipoor, and N. Asadi, “Secure Interposer-Based Heterogenegous Integration,” IEEE Design & Test of Computers (D&T), 2022.
  53. N. Vashishta, M M. Hossain, R. Shahriar, F. Rahman, F. Farahmandi, and M. Tehranipoor, “eChain: A Blockchain-enabled Ecosystem for Electronic Device Authenticity Verification,” IEEE Transactions on Computer Electronics (TCE), 2022.
  54. J. He, X. Guo, M. Tehranipoor, A. Vassilev, and Y. Jin, “EM Side Channel in Hardware Security: Attacks and Defenses,” IEEE Design & Test of Computers (D&T), 2022.
  55. A. Stern, H. Wang, F. Rahim, F. Farahmandi, and M. Tehranipoor, “ACED-IT: Assuring Confidential Electronic Design against Insider Threat in a Zero Trust Environment,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems of Integrated Circuits and Systems (TCAD), 2022.
  56. R. Muttaki, R. Mohammadivojdan, H. M. Kamali, M. Tehranipoor, and F. Farahmandi, “HLock+: A Robust and Low Overhead Logic Locking at the High-Level Language,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Oct. 2022.
  57. N. Pundir, S. Aftabjahani, R. Cammarota, M. Tehranipoor, and F. Farahmandi, “Analyzing Security Vulnerabilities Induced by High-level Synthesis,” ACM Journal of Emerging Technologies in Computing Systems (JETC), 2022.
  58. B. Ahmed, K. Bepary, N. Pundir, M. Borza, O. Raikhman, A. Garg, D. Dunchin, A. Cron, M. Abdel-Moneum, F. Farahmandi, F. Rahman, and M. Tehranipoor, “Quantifiable Assurance: From IPs to Platforms,” 2021, https://eprint.iacr.org/2021/1654.pdf
  59. F. Rahman, F. Farahmandi, and M. Tehranipoor, “An End-to-End Bitstream Tamper Attack Against Flip-chip Package,” IACR Cryptology ePrint Archive, 2021, https://eprint.iacr.org/2021/1542.pdf.
  60. B. Park, D. Forte, M. Tehranipoor, and N. Maghari, “A Metal-Via Resistance Based Physical Unclonable Function with Backend Incremental ADC,” IEEE Transactions on Circuits and Systems I (TCAS-I), 2021.
  61. N. Farzana, F. Farahmandi, and M. Tehranipoor, “SoC Security Properties and Rules,” IACR Cryptology ePrint Archive, 2021, https://eprint.iacr.org/2021/1014.pdf.
  62. N. Vashishtha, H. Lu, Q. Shi, D. Woodard, N. Asdi, and M. Tehranipoor, “Detecting Hardware Trojans using Combined Self Testing and Imaging,” IEEE Transactions on CAD (TCAD), 2021.
  63. N. N. Anandakumar, M. S. Hashmi and M. Tehranipoor, “A Primer on FPGA-based Physical Unclonable Functions: Comprehensive Overview of Theory and Architectures“. Integration, the VLSI Journal, Elsevier, 2021.
  64. N. Pundir, F. Rahman, F. Rahman, and M. Tehranipoor, “What is All the FaaS About? Remote Exploitation of FPGA-as-a-Service Platforms,” IACR Cryptology ePrint Archive, 2021, https://eprint.iacr.org/2021/746.pdf.
  65. F. Ganji, U. Boreto, R. Wilson, M. T. Rahman, M. Azhagan, N. Asadi, M. Tehranipoor, D. Woodard, and D. Forte, “Hardware Trust and Assurance through Reverse Engineering: A Tutorial and Outlook from Image Analysis and Machine Learning Perspective,” ACM Journal of Emerging Technologies in Computing Systems (JETC), 2021.
  66. J. Harrison, N. Asadi, and M. Tehranipoor, “On Malicious Implants in PCBs Throughout the Supply Chain,” VLSI Integration Journal, 2021.
  67. H. Wang, H. Li, F. Rahman, M. Tehranipoor, and F. Farahmandi, “SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks,” IEEE Transactions on Computer-Aided Design (TCAD), 2021.
  68. M. T. Rahman, N. F. Dipu, D. Mehta, S. Tajik, M. Tehranipoor, and N. Asadi, “Concealing-Gate: Optical Contactless Probing Resilient Design,” ACM Journal of Emerging Technologies in Computing Systems (JETC), Feb. 2021.
  69. M. S. Rahman, A. Nahiyan, F. Rahman, S. Fazzari, K. Plaks, F. Farahmandi, D. Forte, and M. Tehranipoor, “Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-Guided Attacks,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 26, Issue 4, March 2021.
  70. D. Mehta, H. Lu, O. Paradis, M. Azhagan, T. Rahman, Y. Iskander, Praveen Chawla, D. Woodard, M. Tehranipoor, and N. Asadi, “The Big Hack Explained: Detection and Prevention of PCB Supply Chain Implants,” ACM Journal of Emerging Technologies in Computing Systems (JETC), 2020.
  71. M. Alam, A. Nahiyan, M. Sadi, D. Forte, and M. Tehranipoor, “Soft-HaT: Software-based Silicon Reprogramming for Hardware Trojan Implementation,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2020.
  72. F. Ganji, et. al., “Rock’n’roll PUFs: Crafting Provably Secure PUFs from Less Secure Ones,” Journal of Cryptographic Engineering (JCEN), 2020.
  73. J. Park, S. Cho, T. Lim, and M. Tehranipoor, “QEC: A Quantum Entropy Chip and Its Applications,” IEEE Transactions on VLSI (TVLSI), 2020.
  74. A. Nahiyan, J. Park, M. He, Y. Iskander, F. Farahmandi, and M. Tehranipoor, “SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment using Information Flow Tracking and Pattern Generation,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2020.
  75. Y. Yang, Z. Duan, and M. Tehranipoor, “Identify Spoofing Attack of In-vehicle CAN Bus Based on Deep Features of ECU Fingerprint Signal,” Smart Cities, MDPI, 2020.
  76. M. T. Rahman, M. S. Rahman, H. Wang, S. Tajik, W. Khalil, F. Farahmandi, D. Forte, N. Asadi, and M. Tehranipoor, “Defense-in-Depth: A Recipe for Logic Locking to Prevail,” Integration, the VLSI Journal, 2020.
  77. Z. Guo, M. Tehranipoor, and D. Forte, “Permutation Network De-obfuscation: A Delay-based Attack and Countermeasure Investigation,” ACM Journal on Emerging Technologies in Computing Systems (JETC), 2020.
  78. H. Wang, Q. Shi, D. Forte, and M. Tehranipoor, “A Physical Design Flow against Front-side Probing Attacks by Internal Shielding,” IEEE Transactions on Computer-Aided Design (TCAD), 2020.
  79. A. Stern, J. Ulberto, Fahim Rahman, D. Forte, and M. Tehranipoor, “EMFORCED: EM-Based Fingerprinting Framework for Remarked and Cloned Counterfeit IC Detection using Machine Learning Classification,” IEEE Transactions on VLSI (TVLSI), 2020.
  80. N. Pundir, M. Tehranipoor, and F. Rahman, “RanStop: A Hardware-Assisted Runtime Crypto-Ransomeware Detection Technique,” 2020, arXiv, https://arxiv.org/abs/2011.12248
  81. B. Shakya, X. Xu, M. Tehranipoor, and D. Forte, “Defeating CAS-Unlock,” IACR Cryptology ePrint Archive, 2020, https://eprint.iacr.org/2020/324.pdf
  82. H. Lu, D. Mehta, O. Paradis, N. Asadizanjani, M. Tehranipoor, and D. L. Woodard, “FICS-PCB: A Multi-Modal Image Dataset for Automated Printed Circuit Board Visual Inspection,” IACR Cryptology ePrint Archive, https://eprint.iacr.org/2020/366, March 2020.
  83. B. Shakya, X. Xu, M. Tehranipoor, D. Forte, “CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme,” Transactions on Cryptographic Hardware and Embedded Systems (TCHES), 2020.
  84. T. Hoque, K. Yang, R. Karam, Shahin Tajik, D. Forte, M. Tehranipoor, and S. Bhunia, “Hidden in Plaintext: An Obfuscation-based Countermeasure against FPGA Bitstream Tampering Attacks,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2019.
  85. F. Ganji, D. Forte, N. Asadizanjani, M. Tehranipoor, D. Woodard, “The power of IC Reverse Engineering for Hardware Trust and Assurance”, Electronic Device Failure Analysis (EDFA), May 2019.
  86. L. Yu, X. Wang, F. Rahman, and M. Tehranipoor, “Interconnect-based PUF with Signature Uniqueness Enhancement,” IEEE Transactions on VLSI (TVLSI), 2019.
  87. J. Park. F. Rahman, A. Vassilev, D. Forte, and M. Tehranipoor, “Leveraging Side Channel Information for Disassembly and Security,” ACM Journal on Emerging Technologies in Computing Systems (JETC), 2019.
  88. M. T. Rahman, S. Tajik, M. S. Rahman, M. Tehranipoor and N. Asadizanjani, “The Key is Left under the Mat: On the Inappropriate Security Assumption of Logic Locking Schemes,” IACR Cryptology ePrint Archive, https://eprint.iacr.org/2019/719, 2019
  89. M Tanjidur Rahman, M Sazadur Rahman, Huanyu Wang, Shahin Tajik, Waleed Khalil, Farimah Farahmandi, Domenic Forte, Navid Asadizanjani, Mark Tehranipoor, “Defense-in-Depth: A Recipe for Logic Locking to Prevail,” arXiv, https://arxiv.org/abs/1907.08863, 2019
  90. U. Guin, N. Asadi, and M. Tehranipoor, “Standards for Hardware Security,” Mobile Computing and Communications, vol. 23, issue 1, pp. 5-9, March 2019.
  91. Y. Han, X. Wang and M. Tehranipoor, “System-Level Counterfeit Detection Using On-Chip Ring Oscillator Array,” IEEE Transactions on VLSI (TVLSI), 2019.
  92. M. Alam, M. Tehranipoor, and D. Forte, “Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling,” IEEE Transactions on VLSI (TVLSI), 2019.
  93. H. Shen, N. Asadi, D. Forte, M. Tehranipoor, “Nanopyramid: An Optical Scrambler Against Backside Probing Attacks,” Journal of Hardware and Systems Security (HaSS), 2019.
  94. B. Shakya, H. Chen, M. Tehranipoor, and D. Forte, “Covert Gates: Protecting Integrated Circuits with Undetectable Camouflaging,” IACR Trans. on Cryptographic Hardware and Embedded Systems (TCHES), 2019.
  95. N. Karimian, D. Woodard, M. Tehranipoor, and D. Forte, “Unlock Your Heart: Next Generation Biometric in Resource-Constrained Healthcare Systems and IoT,” IEEE Access, Vol. 7, Issue 1, pp. 49135-49149, Dec. 2019.
  96. H. Wang, Q. Shi, D. Forte, and M. Tehranipoor, “Probing Assessment Framework and Evaluation of Anti-probing Solutions,” IEEE Transactions on VLSI (TVLSI), 2019.
  97. X. Xu, F. Rahman, B. Shakya, A. Vassilev, D. Forte, and M. Tehranipoor, “Electronic Supply Chain Integrity Enabled by Blockchain,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2019.
  98. K. Yang, U. Botero, H. Shen, D. Woodard, D. Forte, “UCR: An Unclonable Environmentally-Sensitive Chipless RFID Tag for Protecting Supply Chain,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2018.
  99. Q. Shi, M. Tehranipoor, and D. Forte, “Obfuscated Built-In Self-Authentication with Secure and Efficient Wire-Lifting,” IEEE Transactions on Computer-Aided Design (TCAD), 2018.
  100. X. Xu, S. Keshavarz, D. Forte, M. Tehranipoor, and D. Holcomb, “Bimodal Oscillation as a Mechanism for Automotive Majority Voting in PUFs,” IEEE Transactions on VLSI (TVLSI), 2018.
  101. N. Karimian, Z. Guo, F. Tehranipoor, D. Woodard, M. Tehranipoor, and D. Forte, “Noise Aware Biometric Key Generation in Resource-Constrained Systems and IoT,” IEEE Transactions on Signal Processing, 2018.
  102. U. Botero, M. Tehranipoor, and D. Forte, “Upgrade/Downgrade: Efficient and Secure Legacy Electronic System Replacement,” IEEE Design & Test of Computers (D&T), 2018.
  103. D. Zhang, X. Wang, T. Rahman, and M. Tehranipoor, “An On-Chip Dynamically-Obfuscated Wrapper for Protecting Supply Chain Against IP and IC Piracy,” IEEE Transactions on VLSI (TVLSI), 2018.
  104. S. Amir, B. Shakya, X. Xu, Y. Jin, S. Bhunia, M. Tehranipoor, D. Forte, “Development and Evaluation of Hardware Obfuscation Benchmarks,” Journal of Hardware and Systems Security (HaSS), 2018.
  105. N. Vashistha, M. T. Rahman, H. Shen, D. Woodard, N. Asadi and M. Tehranipoor, “Detecting Hardware Trojans Inserted by Untrusted Foundry using Physical Inspection and Advanced Image Processing Techniques,” Journal of Hardware and Systems Security (HaSS), 2018.
  106. A. Nahiyan, F. Farahmandi, P. Mishra, D. Forte, and M. Tehranipoor, “Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks,” IEEE Transactions on Computer-Aided Design (TCAD), 2018.
  107. K. Yang, D. Forte, and M. Tehranipoor, “ReSC: An RFID-Enabled Solution for Defending IoT Supply Chain,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2018.
  108. M. Alam, S. Choudhury, B. Park, D. Munzer, N. Maghari, M. Tehranipoor, and D. Forte, “Challenges and Opportunities in Analog and Mixed Signal (AMS) Integrated Circuit (IC) Security,” Journal of Hardware and Systems Security (HaSS), 2018.
  109. Z. Guo, X. Xu, T. Rahman, M. Theranipoor, and D. Forte, “SCARe: An SRAM based Countermeasure Against IC Recycling Framework,” IEEE Transactions on VLSI (TVLSI), 2018.
  110. X. Wang, D. Zhang, M. He, and M. Tehranipoor, “Secure Scan and Test Using Obfuscation Throughout Supply Chain,” IEEE Trans. On Computer-Aided Design (TCAD), 2018.
  111. E. Principe, N. Asadi, D. Forte, R. Chivas, M. DiBattista, and S. Silverman, “Plasma FIB Deprocessing of Integrated Circuits from the Backside,” Electronic Device Failure Analysis (EDFA), 2018.
  112. K. Yang, H. Shen, D. Forte, S. Bhunia, and M. Tehranipoor, “Hardware-Enabled Pharmaceutical Supply Chain Security,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2018.
  113. S. Ray, S. Bhunia, and M. Tehranipoor, “System-on-Chip Platform Security Assurance: Architecture and Validation,” Proceedings of IEEE, vol. 106, Issue 1, page 21-37, 2018.
  114. T. Rahman, A. Hosey, J. Carrol, D. Forte, and M. Tehranipoor, “Systematic Correlation and Cell Neighborhood Analysis of SRAM-PUF for Robust and Unique Key Generation,” Journal of Hardware and Systems Security (HaSS), 2017.
  115. F. Rahman, B. Shakya, X. Xu, D. Forte, and M. Tehranipoor, “Security Beyond CMOS: Fundamentals, Applications, and Roadmap,” IEEE Transactions on VLSI (TVLSI), 2017.
  116. M. Sadi, G. Contreras, J. Chen, L. Winemberg, and M. Tehranipoor, “Design of Reliable SoCs with BIST Hardware and Machine Learning,” IEEE Transactions on VLSI (TVLSI), 2017.
  117. H. Shen, F. Rahman, B. Shakya, X. Xu, M. Tehranipoor, and D. Forte, “Poly-Si Based Physical Unclonable Functions,” IEEE Transactions on VLSI (TVLSI), 2017.
  118. H. Wang, Q. Shi, D. Forte, M. Tehranipoor, “Probing Attacks on Integrated Circuits: Challenges and Research Opportunities,” IEEE Design & Test of Computers, 2017.
  119. M. Alam, M. Tehranipoor, and U. Guin, “TSensors Vision, Infrastructure, and Security Challenges in Trillion Sensor Era,” Journal of Hardware and Systems Security (HaSS), 2017.
  120. M. He and M. Tehranipoor, “An Access Mechanism for Embedded Sensors in Modern SoCs,” Journal of Electronics Testing: Theory and Applications (JETTA), 2017.
  121. T. He, G. Contreras, D. Tran, L. Winemberg, and M. Tehranipoor, “Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications,” IEEE Transactions on VLSI (TVLSI), 2017.
  122. M. Tehranipoor, U. Guin, and S. Bhunia, “Invasion of the Hardware Snatchers: Fake Hardware Could Open the Door to Malicious Malware and Critical Failure,” IEEE Spectrum, 2017.
  123. B. Shakya, H. Salmani, D. Forte, S. Bhunia, and M. Tehranipoor, “Benchmarking of Hardware Trojans and Maliciously Affected Circuits,” Journal of Hardware and Systems Security (HaSS), 2017.
  124. M. Alam, N. Asadi, M. Tehranipoor, and D. Forte, “Impact of X-ray Tomography on the Reliability of Integrated Circuits,” IEEE Transaction on Device and Materials Reliability, 2017.
  125. Z. Guo, J. Di, M. Tehranipoor, and D. Forte, “Obfuscation based Protection Framework Against Printed Circuit Boards Piracy Violations,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2017.
  126. N. Asadi, M. Tehranipoor, and D. Forte, “PCB Reverse Engineering Using Non-destructive X-ray Tomography and Advanced Image Processing,” IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), 2017.
  127. U. Guin, S. Bhunia, D. Forte, and M. Tehranipoor, “SMA: A System-Level Mutual Authentication for Protecting Electronic Hardware and Firmware,” IEEE Transactions on Dependable and Secure Computing (TDSC), 2016.
  128. K. Yang, D. Forte, and M. Tehranipoor, “CDTA: A Comprehensive Solution for Counterfeit Detection, Traceability and Authentication in IoT Supply Chain,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016.
  129. N. Karimian, Z. Guo, M. Tehranipoor, and D. Forte, “Highly Reliable Key Generation from Electrocardiogram (ECG),” IEEE Transactions on Biomedical Engineering (TBME), 2016.
  130. X. Wang, P. Jiao, M. Sadi, L. Winemberg, and M. Tehranipoor, “TRO: An On-chip Ring Oscillator Based GHz Transient IR-Drop Monitor,” IEEE Trans. On Computer-Aided Design (TCAD), 2016.
  131. M. Sadi, L. Winemberg, S. Kannan, and M. Tehranipoor, “SoC Speed Binning Using Machine Learning and On-chip Slack Sensors,” IEEE Trans. On Computer-Aided Design (TCAD), 2016.
  132. K. Xiao, A. Nahiyan, and M. Tehranipoor, “ Security Rule Checking in IC Design,” IEEE Computer Magazine, 2016.
  133. J. Wurm, Y. Jin, Y. Liu, S. Hu, K. Heffner, F. Rahman, and M. Tehranipoor, “Introduction to Cyber Physical System Security: A Cross-Layer Perspective,” IEEE Trans. On Multi-Scale Computing Systems (TMSCS), 2016.
  134. Y. Xie, C. Bao, C. Serafy, T. Lu, A. Srivastava, and M. Tehranipoor, “Security and Vulnerability Implications of 3D ICs,” IEEE Trans. On Multi-Scale Computing Systems (TMSCS), 2016.
  135. K. Xiao, D. Forte, Y. Jin, R. Karri, S. Bhunia, and M. Tehranipoor, “Hardware Trojans: Lessons Learned After One Decade of Research,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016. (made the 2016 most notable computing articles list, Computingreviews.com). The paper also received the Best Paper Award from TODAES.
  136. U. Guin, Q. Shi, D. Forte, and M. Tehranipoor, “FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016.
  137. Q. Shi, X. Wang, L. Winemberg, and M. Tehranipoor, “On-Chip Sensor Selection for Effective Speed-Binning,” Int. Journal on Analog Integrated Circuits and Signal Processing, 2016.
  138. H. Salmani and M. Tehranipoor, “Vulnerability Analysis of a Circuit Layout to Hardware Trojan Insertion,” IEEE Transactions on Information Forensics & Security (TIFS), 2016.
  139. M. Sadi and M. Tehranipoor, “Design of a Network of Digital Sensor macros for Extracting Power Supply Noise Profile in SoCs,” IEEE Transactions on VLSI (TVLSI), 2016.
  140. X. Wang, D. Zhang, D. Su, L. Winemberg, and M. Tehranipoor, “A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits,” IEEE Transactions on VLSI (TVLSI), 2016.
  141. T. Rahman, F. Rahman, D. Forte, and M. Tehranipoor, “An Aging-Resistant RO-PUF for Reliable Key Generation,” IIEEE Transactions on Emerging Topics in Computing (TETC), 2015.
  142. U. Guin, D. Forte, and M. Tehranipoor, “Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling,” IEEE Transactions on VLSI (TVLSI), 2015.
  143. S. Quadir, J. Chen, D. Forte, N. Asadi, S. Shahbaz, L. Wang, J. Chandy, and M. Tehranipoor, “A Survey on Chip to System Reverse Engineering,” ACM Journal on Emerging Technologies in Computing Systems (JETC), 2015.
  144. S. Kelly, X. Zhang, M. Tehranipoor, and A. Ferraiuolo, “Detecting Hardware Trojans using On-chip Sensors in an ASIC Design,” Journal of Electronic Testing: Theory and Applications (JETTA), 2015.
  145. X. Wang, D. Tran, S. George, L. Winemberg, N. Ahmed, S. Palosh, L. Dobia, M. Tehranipoor, “Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor,” IEEE Transactions on CAD (TCAD), 2015.
  146. K. Xiao, D. Forte, and M. Tehranipoor, “A Novel Built-In Self-Authentication Technique to Prevent Inserting Hardware Trojans,” IEEE Transactions on CAD (TCAD), 2014.
  147. A. Tomita, X. Wen, Y. Sato, S. Kajihara, K. Miyase, S. Holst, P. Girard, M. Tehranipoor, L.T. Wang, “On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST,” IEICE Transactions, 2014.
  148. U. Guin, K. Huang, D. DiMase, J. Carulli, M. Tehranipoor, Y. Makris, “Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain,” Proceedings of IEEE, 2014.
  149. Z. Collier, D. DiMase, S. Walters, M. Tehranipoor, J. Lambert, and I. Linkov, “Risk-Based Cybersecurity Standards: Policy Challenges and Opportunities,” IEEE Computer Magazine, 2014.
  150. U. Guin, D. DiMase, and M. Tehranipoor, “A Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead,” Journal of Electronic Testing: Theory and Applications (JETTA), 2014.(Most Downloaded Article in 2014)
  151. U. Guin, D. DiMase, and M. Tehranipoor, “A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment,” Journal of Electronic Testing: Theory and Applications (JETTA), 2014.
  152. A. Markman, B. Javidi, and M. Tehranipoor, “Photon-Counting Security Tagging and Verification Using Optically Encoded QR Codes,” IEEE Photonics Journal, 2013.
  153. X. Zhang and M. Tehranipoor, “Design of On-chip Light-weight Sensors for Effective Detection of Recycled ICs,,” IEEE Transactions on VLSI (TVLSI), 2013.
  154. F. Bao, K. Peng, M. Tehranipoor, and K. Chakrabarty, “Generation of Effective 1-Detect TDF Patterns for Detecting Small-Delay Defects,,” IEEE Trans. on CAD (TCAD), 2013.
  155. S. Wang and M. Tehranipoor, “A Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated Circuits,” IEEE Transactions on VLSI (TVLSI), 2013.
  156. W. Zhao, J. Ma, M. Tehranipoor, and S. Chakravarty, “Power-Safe Application of TDF Patterns to Flip-Chip Designs during Wafer Test,” ACM Transactions on Design Automation of Electronic Systems (TODAES), 2013.
  157. M. Li, A. Davoodi, and M. Tehranipoor, “A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection,” IEEE Design & Test, 2013.
  158. K. Xiao, X. Zhang, and M. Tehranipoor, “A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay,” IEEE Design & Test, 2013.
  159. F. Bao, K. Peng, M. Yilmaz, K. Chakrabarty, L. Winemberg, and M. Tehranipoor, “Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults,” Journal of Electronic Testing: Theory and Applications (JETTA), 2013.
  160. J. Chen, S. Wang, and M. Tehranipoor, “Critical-Reliability Path Identification and Delay Analysis,” ACM Journal on Emerging Technologies in Computing Systems (JETC), 2013.
  161. X. Zhang, A. Ferraiuolo, and M. Tehranipoor, “Detection of Hardware Trojans using a Combined Ring Oscillator Network and Off-chip Transient-Power Analysis,” ACM Journal on Emerging Technologies in Computing Systems (JETC), 2013
  162. J. Villasenor and M. Tehranipoor, “ The Hidden Dangers of Chop-Shop Electronics,” IEEE Spectrum, October 2013.
  163. K. Peng, M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects,”IEEE Transactions on VLSI (TVLSI), 2012.
  164. M. Abramovici, et. al., “Protecting Against Hardware Trojan Attacks: Towards a Comprehensive Solution,” IEEE Design & Test of Computers, 2012.
  165. W. Zhao, M. Tehranipoor, and S. Chakravarty, “Ensuring Power-Safe Application of Test Patterns Using An Effective Gating Approach Considering Current Limits,” Journal of Low Power Electronics (JOLPE), 2012.
  166. X. Wang, M. Tehranipoor, S. George, D. Tran and L. Winemberg, “Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurement“, IEEE Transactions on VLSI (TVLSI), 2012.
  167. H. Salmani, W. Zhao, M. Tehranipoor, S. Chakravarty, P. Girard, and X. Wen, “Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns,” Journal of Low Power Electronics (JOLPE), 2012.
  168. H. Salmani, M. Tehranipoor, and J. Plusquellic, “A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time,” IEEE Transactions on VLSI (TVLSI), 2012.
  169. H. Salmani and M. Tehranipoor, “A Layout-Aware Approach for Improving Localized Switching to Detect Hardware Trojans in Digital Integrated Circuits,” Transactions on Information Forensics & Security (TIFS), 2012.
  170. J. Ma, M. Tehranipoor, and P. Girard, “A Layout-Aware Pattern Grading Procedure for Critical Paths Testing Considering Crosstalk and Power Supply Noise,” Journal of Electronics Testing: Theory and Applications (JETTA), 2012.
  171. J. Ma and M. Tehranipoor, “Layout-Aware Critical Path Delay Test under Maximum Power Supply Noise Effects,” IEEE Transactions on CAD (TCAD), 2011.
  172. C. Lamech, R. Rad, J. Plusquellic, and M. Tehranipoor, “An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities,” IEEE Transactions on Information Forensics & Security (TIFS), 2011.
  173. M. Tehranipoor, H. Salmani, X. Zhang, X. Wang, R. Karri, J. Rajendran, and K. Rosenfeld, “Trustworthy Hardware: Trojan Detection Solutions and Design-for-Trust Challenges,” IEEE Computer Magazine, 2011.
  174. M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “Adaptation and Evaluation of the Output-Deviations Metric to Target Small-Delay Defects in Industrial Circuits,” IEEE Design and Test of Computers, 2010.
  175. R. Karri, J. Rajendran, K. Rosenfeld, and M. Tehranipoor, “Trustworthy Hardware: Identifying and Classifying Hardware Trojans,” IEEE Computer Magazine, 2010.
  176. M. Tehranipoor and K. Butler, “Power Supply Noise: A Survey on Effects and Research,” in IEEE Design and Test of Computers, 2010.
  177. F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, X. Wen, and N. Ahmed, “A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes,” Journal of Low Power Electronics (JOLPE), 2010.
  178. M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “Test-Pattern Selection Small-Delay Defects in Very-Deep Submicron Integrated Circuits,” IEEE Transactions on CAD, 2010.
  179. N. Ahmed and M. Tehranipoor, “A Novel IR-drop Tolerant Transition Delay Fault Test Pattern Generation Procedure,” Journal of Low Power Electronics (JOLPE), 2010.
  180. M. Tehranipoor and F. Koushanfar, “A Survey of Hardware Trojan Taxonomy and Detection,” IEEE Design and Test of Computers, 2010.
  181. N. Ahmed and M. Tehranipoor, “A Novel Faster-than-at-speed Transition Delay Test Method Considering IR-drop Effects,” IEEE Trasactions on CAD, 2010.
  182. R. Rad, J. Plusquellic, and M. Tehranipoor, “A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans under Real Process and Environmental Conditions,” IEEE. Transactions on VLSI (TVLSI), 2009
  183. K. Miyase, X. Wen, H. Furukawa, Y. Yamato, S. Kajihara, P. Girard, L.-T. Wang, and M. Tehranipoor, “High Launch Switching Activity Reduction in At- Speed Scan Testing using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme,” IEICE Trans. Fundamentals/Commun./Electron/Inf. & Syst., vol. E85-A/B/C/D, 2009.
  184. J. Lee and M. Tehranipoor, “Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity,” Journal of Low Power Electronics (JOLPE), Vol. 4, No. 3, 2008.
  185. M. Tehranipoor and R. Rad, “Defect Tolerance for Nanoscale Crossbar-based Devices,” in IEEE Design & Test of Computers, 2008.
  186. R. Rad and M. Tehranipoor, “SCT: A Novel Approach For Testing and Configuring Nanoscale Devices,” in ACM Journal on Emerging Technologies in Computing Systems (JETC), 2008.
  187. M. Nourani, M. Tehranipoor and N. Ahmed, “Low-Transition Test Pattern Generation for BIST-Based Applications,” IEEE Transactions on Computers, vol. 57, no. 3, pp. 303-315, March 2008.
  188. J. Lee, M. Tehranipoor, C. Patel and J. Plusquellic, “Securing Designs Against Scan-Based Side-Channel Attacks,” IEEE Transactions on Dependable and Secure Computing (TDSC), vol. 4, no. 4, Oct.-Dec. 2007. .
  189. R. Rad and M. Tehranipoor, “Evaluating Area and Performance of a Hybrid FPGA with Nanoscale Clusters and CMOS Routing,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 3, no. 3, Nov. 2007.
  190. M. ElShoukry and M. Tehranipoor and C.P. Ravikumar, “A Critical-Path Aware Partial Gating Approach for Test Power Reduction,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 12 , Issue 2, April 2007.
  191. N. Ahmed, M. Tehranipoor, C.P. Ravikumar and K. Butler, “Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), vol. 26, no. 5, pp. 896-906, May 2007.
  192. M. Tehranipoor and R. M.P. Rad, “Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based NanoFabrics,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), vol. 26, no. 5, 943-958, May 2007.
  193. N. Ahmed and M. Tehranipoor, “Improving Quality of Transition Delay Test Using Hybrid Scan-Based Technique,” IEEE Design and Test of Computers, 2006.
  194. D. Acharyya, A. Singh, M. Tehranipoor, C. Patel and J. Plusquellic, “Quiescent Signal Analysis: a Multiple Supply Pad IDDQ Method,” IEEE Design and Test of Computers, vol. 23, no. 4, pp. 278-293, 2006.
  195. M. Tehranipoor, M. Nourani and K. Chakrabarty, “Nine-Coded Compression Technique for Testing Embedded Cores in SoCs,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 13, no. 6, pp. 719-731, June 2005.
  196. M. Nourani and M. H. Tehranipour, “RL-Huffman Encoding for Test Compression and Power Reduction in Scan Application,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 10, no. 1, pp. 91-115, Jan. 2005.
  197. M. H. Tehranipour, N. Ahmed and M. Nourani, “Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (CAD/ICAS), vol. 23, issue 5, pp. 800-811, May 2004.
  198. M. H. Tehranipour, S. M. Fakhraie, Z. Navabi and M. R. Movahedin, “A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 20, pp. 155-168, April 2004.
  199. M. H. Tehranipour, S. M. Fakhraie, M. Nourani, M. R. Movahedin and Z. Navabi, “Embedded Test for Processor and Memory Cores in System-on-Chips,” International Journal of Science and Technology, vol. 10, no. 4, pp. 486-494, Oct. 2003.