Home > Publications > Conference Papers

Conference Papers

  1. N. Alam, M. Tehranipoor, F. Farahmandi, “TRIDENT: AI-Powered Threat Modeling and Property-Driven Security in Chiplet-Based System-in-Package Architectures,” GomacTech, 2026.
  2. M. M. M. Rahman, S. K. Saha, M. Tehranipoor, and F. Farahmandi, “Automating Security Monitoring Event Generation for SoCs Using Large Language Models,” GomacTech, 2026.
  3. S. Saha, A. Alhurubi, T. Rahman, S. K. Saha, F. Farahmandi, and M. Tehranipoor, “Emulation-based Fuzzing for System-level Vulnerability Detection,” GomacTech, 2026.
  4. S. Tarek, D. Saha, S. K. Saha, M. Tehranipoor, and F. Farahmandi, “Threat2SVA: Threat Model and CWE-Aware Security Assertion Generation Using LLM,” GomacTech, 2026.
  5. M. A. Hasan, D. Saha, K. T. Hasan, N. Alam, A. Uddin, S. K. Saha, M. Tehranipoor and F. Farahmandi, “LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification,” Design Automation and Test in Europe (DATE), 2026.
  6. S. Saha, A. Alhurubi, T. Rahman, H. Al Shaikh, S. K. Saha, F. Farahmandi, M. Tehranipoor, “GEmFuzz: Uncovering System-Level Vulnerabilities in SoCs via Emulation-Based Grey-Box Fuzzing,” the Asia and South Pacific Design Automation Conference (ASP-DAC), 2026.
  7. A. Vafaei, S. K. Saha, M. Tehranipoor and F. Farahmandi, “Cultivating Security: Debug Authentication for Ensuring the Security of SoC’s Root of Trust,” IEEE VLSI-SoC, 2025.
  8. T. Rahman, S. Saha, S. K. Saha, F. Farahmandi and M. Tehranipoor, “EmFIA: A Novel Emulation-based Fault Injection Vulnerability Assessment Framework at RTL Level,” IEEE VLSI-SoC, 2025.
  9. Z. Ibnat, P. E. Calzada, D. Saha, H. Al-Shaikh, S. K. Saha, J. Zhou, F. Farahmandi, and M. Tehranipoor, “Trusting the machine: How secure is LLM-generated RTL code?” in International Symposium on Machine Learning for CAD (ML-CAD), 2025.
  10. L. Rahman, A. M. Shuvo, J. Zhou, F. Farahmandi and M. Tehranipoor, “RunSiP: Property-Based Runtime Security Monitoring in Heterogeneous System-in-Package,” nternational Symposium for Testing and Failure Analysis (ISTFA), 2025.
  11. P. Sarker, T. Kan, J. Liang, O. Tuncer, B. He, Z. Lu, S. Mallu, L. Lin, N. Chang, R. Hasegawa, K. Monta, M. Nagata, F. Farahmandi and M. Tehranipoor, “ML-EMFI : A Machine Learning-Driven Pre-Silicon Electromagnetic Fault Injection Security Evaluation for Robust IC Design,” IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST), 2025.
  12. A. M. Shuvo, L. Rahman, J. Zhou, F. Farahmandi and M. Tehranipoor, “A System-Aware Remote Fault-Injection Attack Detection & Mitigation for Secure Heterogeneous Systems,” IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST), 2025 (Best Paper Award).
  13. S. Tarek, D. Saha, S. Saha, M. Tehranipoor, and F. Farahmandi, “SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation”, IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2025.
  14. H. Li, H. Rahman, A. Basu, R. Hassan, F. Farahmandi, M. Tehranipoor, “Physical Model-Assisted Secure Software Execution Against Fault-Injection Attacks,” GpmacTech, 2025
  15. D. Saha, S. K. Saha, J. Zhou, M. Tehranipoor and F. Farahmandi, “Enhancing Hardware Security: Detecting Vulnerabilities in HDL Codes Using Fine-Tuned Large Language Model”, GOMACTech, 2025.
  16. P. Sarker, R. Hassan, L. Ling, N. Chang, F. Farahmandi, M. Tehranipoor, “ML-PREMISE: A Machine Learning-Driven Pre-Silicon Electromagnetic Fault Injection Security Evaluation for Robust IC Design” GomacTech, 2025.
  17. S. Hague, J. Zhou, F. Farahmandi, and M. Tehranipoor, “Leveraging Advanced Packaging for IP Protection in Heterogeneous AI Hardware,” IEEE 75th Electronics Components and Technology Conference (ECTC), 2025.
  18. L. Rahman, A. Mazumder, J. Zhou, M. Tehranipoor, and F. Farahmandi, “SiPMeter: Active Hardware Metering for Heterogeneously Integrated System-in-Packages (SiPs),” IEEE 75th Electronics Components and Technology Conference (ECTC), 2025.
  19. A. Mazumder, S. Ul. Islam, J. Zhou, F. Farahmandi, M. Tehranipoor, “Enhancing Runtime Security in Heterogeneous System-in-Package Through A Chiplet-Based Root-of-Trust,” IEEE 75th Electronics Components and Technology Conference (ECTC), 2025.
  20. S. Tarek, D. Saha, S. Saha, M. Tehranipoor, and F. Farahmandi, “SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation”, IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2025.
  21. J. Harrison, N. Jessurun, and M. Tehranipoor, “SoK: A Security Architect’s View of Printed Circuit Board Attacks,” USENIX, 2025.
  22. M. S. Haque, A. Uddin, J. Zhou, H. M. Kamali, F. Farahmandi, and M. Tehranipoor, “NoXLock: SiP Activation and Licensing through Obfuscated On-Chip Network and Fuzzy Traffic,” the Asia and South Pacific Design Automation Conference (ASP-DAC), 2025. Best Paper Candidate.
  23. A. Uddin, S. K. Saha, F. Farahmandi, and M. Tehranipoor, “Case Study: Fault-Injection Vulnerability Assessment at RTL Level,” IEEE Physical Assurance and Inspection of Electronics (PAINE), 2024.
  24. M. Monjil, J. Zhou, N. Varshney, N. Asadi, F. Farahmandi, and M. Tehranipoor, “ChiPICA: Chiplet Physical Inspection Certification Authority for Trust Verification in Heterogeneous Integration,” IEEE Physical Assurance and Inspection of Electronics (PAINE), 2024. Best Paper Candidate.
  25. S. Islam, S. Khan, F. Farahmandi, M. Tehranipoor, and N. Asadi, “CAKE-SiP: Chiplet Authenticate & Key Exchange for Secure Provisioning in System-in-Package,” IEEE Physical Assurance and Inspection of Electronics (PAINE), 2024. Best Poster Candidate.
  26. G. Haidar, S. Islam, J. Zhou, K. Z. Azar, M. Tehranipoor, and F. Farahmandi, “SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits,” International Test Confeence (ITC), 2024.
  27. B. Ahmed, J. Zhou, S. Saha, S. Aftabjahani, M. Tehranipoor, and F. Farahmandi, “Continuity in Security: Leveraging LLM for Translating Security Properties Across Hardware Designs,” Int. Conference on Very Large-Scale Integration (VLSI-SoC), 2024. Best Paper Candidate.
  28. P. Sarker, U. Das, N. Vershney, M. Monjil, J. Zhou, M. Tehranipoor, F. Farahmandi, “OPTI-WM: Optical Probing for Enhanced IP Watermark Identification in SoC Using Covert FSM to Combat IP Piracy,” International Symposium for Testing and Failure Analysis (ISTFA), 2024.
  29. A. M. Shuvo, S. Sami, L. Rahman, J. Zhou, K. Z. Azar, F. Farahmandi, M. Tehranipoor, “SYSFID: System-Aware Fault-Injection Attack Detection for System-in-Package Architectures,” International Symposium for Testing and Failure Analysis (ISTFA), 2024.
  30. P. Calzada, S. Ul Islam Sami, J. Zhou, K. Zamiri Azar, F. Farahmandi, M. Tehranipoor, “HI-SST: Safeguarding SiP Authenticity through Secure Split-Test in Heterogeneous Integration,” IEEE Computer Society Annual Symosium on VLSI (ISVLSI), 2024.
  31. J. Harrison, N. Jessurun, R. R. Dos Santos, S. Ghosh, N. Asadi, and M. Tehranipoor, “Analysis of Etcher Configuration on Part Marking Characteristics for Counterfeit Identification,” International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2024.
  32. B. Ahmed, S. Rahman, K. Z. Azar, F. Farahmandi, F. Rahman and M. Tehranipoor, “SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented Estimation,” GLSVLSI, 2024.
  33. S. U. I Sami, S. Saha, J. Zhuo, F. Rahman, F. Farahmandi, and M. Tehranipoor, “SAP: Silicon Authentication Platform for System-on-Chip Supply Chain Vulnerabilities” IEEE Int. Symposiu, on Performance Analysis of Systems and Software (ISPASS), 2024.
  34. D. Saha, K. Yahyaei, S. Saha, M. Tehranipoor, and F. Farahmandi, “Empowering Hardware Security with LLM: The Development of a Vulnerable Hardware Database,” IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST), 2024.
  35. G. I. Haidar, K. Z. Azar, H. M. Kamali, M. Tehranipoor, and F. Farahmandi, “GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package,” Design Automation Conference (DAC), 2024.
  36. H. Li, L. Lin, N. Chang, S. Chowdhury, M. Tehranipoor, K. Monta, and M. Nagata, “ML-Based Optimal Virtual Placement Exploration for EM Side-Channel Mitigation” DesignCon, 2024 (Best Paper Candidate).
  37. M. Sami, K. Azar, H. Kamali, F. Farahmandi, and M. Tehranipoor, “PQC-HIL PQC-enabled Chiplet authentication and Key Exchange in Heterogeneous Integration,” Electronics Components and Technology (ECTC), 2024.
  38. N. Mondol, A. Vafaei, K. Z. Azar, F. Farahmandi, and M. Tehranipoor, “RL-TPG: Automated Pre-silicon Security Verification through Reinforcement Learning-based Test Pattern Generation,” Design Automation and Test in Europe (DATE), 2024.
  39. H. Li, L. Lin, N. Chang, S. Chowdhury, D. McGuire, B. Novakovic, N. Agata, Y. Li, Pramod MS, C. Xi, Q. Jin, N. Asadi, and M. Tehranipoor, “Photon Emission Modeling and Machine-Learning Assisted Pre-Silicon Optical Side-channel Simulation,” IEEE Int. Hardware-Oriented Security and Trust (HOST), 2024.
  40. S. R. Rajendran, F. Farahmandi, and M. Tehranipoor, “CAD Tools Pathways in Hardware Security,” International Conference on VLSI Design (VLSID), 2024.
  41. N. F. Dipu, M. M. Hossain, K. Z. Azar, F. Farahmandi, and M. Tehranipoor, “FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection,” Asian and South Pacific Conference on Design Automation Conference (ASP-DAC), 2024.
  42. M. R. Muttaki, H. M. Kamali, M. Tehranipoor and F. Farahmandi, “PALLET: Protecting Analog Devices using a Last-Level Edit Technique,” IEEE Conference on Physical Assurance and inspection of Electronics (PAINE), 2023.
  43. M. S. Ul Haque, R. Guo, M. Sazadur Rahman, H. M. Kamali, F. Farahmandi and M. Tehranipoor, “SHI-Lock: Enabling Co-Obfuscation for Secure Heterogeneous Integration against RE and Cloning,” IEEE Conference on Physical Assurance and Inspection of Electronics (PAINE), 2023.
  44. M. Hossain, N. D. Farzana, K. Z. Azar, F. Rahman, and M. Tehranipoor, “TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing,” Int. Conference on Computer-Aided Design (ICCAD), 2023.
  45. R. Kibria, F. Farahmandi and M. Tehranipoor, “ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction,” International Test Conference (ITC), 2023 (Best Paper Candidate and Honorable Mention).
  46. P. P. Sarker, U. Das, M. Monjil, H. M. Kamali, F. Farahmandi, and Mark Tehranipoor, “GEM-Water: Generation of EM-based Watermark for SoC IP Validation with Hidden FSMs,” International Symposium for Testing and Failure Analysis (ISTFA), 2023.
  47. S. Rahman, N. Varshney, F. Farahmandi, N. Asadi, and M. Tehranipoor, “LLE: Mitigating IC Piracy and Reverse Engineering by Last Level Edit,” International Symposium for Testing and Failure Analysis (ISTFA), 2023.
  48. H. Al-Shaikh, M. B. Monjil, K. Z. Azar, F. Farahmandi, M. Tehranipoor, and F. Rahman, “QuardTropy: Detecting and Quantifying Unathorized Information Leakage in Hardware Designs using g-entropy,” IEEE Defect and Fault Tolerant Systems (DFTS), 2023.
  49. M. Monir, K. Z. Azar, F. Farahmandi, and M. Tehranipoor, “EmuFuzzer: Emulation-based Cost Function Guided Fuzzing for SoC Vulnerability Detection,” SRC TECHCON, 2023.
  50. S. Tarek, S. Rajendran, M. Tehranipoor, and F. Farahmandi, “Benchmarking of SoC-level Hardware Vulnerabilities: A Complete Walkthrough,” ISVLSI, 2023.
  51. D. Volya, T. Zhang, N. Alam, M. Tehranipoor, and O. Mishra, “Towards Secure Classical-Quantum Systems,” IEEE Internaional Symposium on Hard-Oriented Security and Trust (HOST), 2023.
  52. Y. Bai, J. Park, M. Tehranipoor, and D. Forte, “Dual Channel EM/Power Attack Using Mutual Information and its Real-time Implementation,” IEEE Internaional Symposium on Hard-Oriented Security and Trust (HOST), 2023.
  53. T. Rahman, K. Bepary, S. Haque, M. Tehranipoor, and F. Rahman, “Design and Security Mitigation of Configurable and Generative Hardware Cryprosystems,” IEEE Dallas Circuits and Systems (DCAS) Conference, 2023.
  54. Z. Ibnat, S. Rahman, M. Tehranipoor, and F. Farahmandi, “ActiWate: Adaptive Design-agnostic Active Watermark for IP Ownership in Modern SoCs,” Design Automation Conference (DAC), 2023.
  55. U. Das, M S. Rahman, N. N. Anandakumar, K. Zamiri Azar, F. Rahman, M. Tehranipoor, and Farimah Farahmandi, “PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates,” IEEE European Test Symposium (ETS), 2023.
  56. T. Zhang, M. Tehranipoor, and F. Farahmandi, “BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering,” IEEE European Test Symposium (ETS), 2023.
  57. B. Ahmed, M. Tehranipoor, and F. Farahmandi, “SoC Security Verification: Challenges and Solutions,” IEEE VLSI Test Symposium (VTS), 2023.
  58. M. M. Rahman, S. M. Rahman, R. Kibria, M. Borza, B. Reddy, A. Cron, F. Rahman, M. Tehranipoor, and F. Farahmandi, “CAPEC: A Cellular Automata Cuided FSM-based IP Authentication Scheme,” IEEE VLSI Test Symposium (VTS), 2023.
  59. T. Zhang, L. Rahman, H. M. Kamali, K. Z. Azar, M. Tehranipoor, and F. Farahmandi, “Fault Injection Detection in Secure Heterogeneous Integration via Power Noise Variations,” Electronic Components and Technology Conference (ECTC), 2023.
  60. M. R. Muttaki, S. Saha, H. M. Kamali, F. Rahman, M. Tehranipoor and F. Farahmandi, “RTLock: IP Protection using Scan-Aware Logic Locking at RTL,” Design, Automation and Test in Europe (DATE), 2023. Nominated for Best Paper Award.
  61. S. R. Rajendran, S. Tarek, B. M. Hicks, H. M. Kamali, F. Farahmandi and M. Tehranipoor, “HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities,” Design, Automation and Test in Europe (DATE), 2023.
  62. R. Guo, M. S. Rahman, H. M. Kamali, F. Rahman, F. Farahmandi and M. Tehranipoor, “EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction,” Design, Automation and Test in Europe (DATE), 2023.
  63. H. M. Kamali, K. Z. Azar, F. Farahmandi and M. Tehranipoor, “SheLL: Shrinking eFPGA Fabrics for Logic Locking,” Design, Automation and Test in Europe (DATE), 2023. Nominated for Best Paper Award.
  64. M. M. Hossain, A. Vafaei, K. Z. Azar, F. Rahman, F. Farahmandi and M. Tehranipoor, “SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing,” Design, Automation and Test in Europe (DATE), 2023. Nominated for Best Paper Award.
  65. M. S. Haque, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Countering Reverse Engineering and Cloning in Heterogeneously Integrated Systems,” GomacTech, 2023.
  66. J. Harrison, Nathan Jessurun, N. Asadi, and M. Tehranipoor, “Exploration of Automated Laser Marking Analysis for Counterfeit IC Identification,” GomacTech, 2023.
  67. M. K. Bepray, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Security Assessment and Modeling of EM Side-Channel Leakage at Gate-Level,” GomacTech, 2023.
  68. E. Tawfik, et. al. “Holistic Secure SoC Design for Resource Constrained Applications,” GomacTech, 2023.
  69. M. Monjil, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Robust Verification for Physical Inspection Based Chiplet Authentication,” GomacTech, 2023.
  70. S. R. Rajendran, M. Tehranipoor, and F. Farahmandi, “An ISA-based Software Snippet Generation for Exploiting Hardware Vulnerabilities,” GomacTech, 2023.
  71. S. Shi, N. Pundir, H. Mardani Kamali, M. Tehranipoor, F. Farahmandi, “SecHLS: Enabling Security Awareness in High-Level Synthesis,” Asian and South Pacific Conference on Design Automation Conference (ASP-DAC), 2023.
  72. H. Al-Shaikh, A. Vafaei, M. Md Mashahedur Rahman, K. Zamiri Azar, F. Rahman, F. Farahmandi, M. Tehranipoor, “SHarPen: SoC Security Verification by Hardware Penetration Test,” Asian and South Pacific Conference on Design Automation Conference (ASP-DAC), 2023.
  73. R. Muttaki, M. Tehranipoor, and F. Farahmandi, “FTC: A Universal Low-Overhead Fault-Injection Attack Detection Solution,” International Symposium for Testing and Failure Analysis (ISTFA), 2022.
  74. N. Pundir, H. Li, L. Lin, N. Chang, “SPILI: Security Properties and Machine Learning Assisted Pre-silicon Laser Fault Injection Assessment,” International Symposium for Testing and Failure Analysis (ISTFA), 2022.
  75. R. Kibria, S. Rahman, F. Farahmandi, and M. Tehranipoor, “RTL-FSMx: Fast and Accurate Finite State Machine Extraction ar the RTL for Security Application,” International Test Conference (ITC), 2022.
  76. U. Das, R. Muttaki, m. Tehranipoor, and F. Farahmandi, “ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features,” International Test Conference (ITC), 2022.
  77. A. Mazumder Shuvo, N. Pundir, J. Park, F. Farahmandi, and M. Tehranipoor, “LDTFI: Layout-Aware Timing Fault-Injection Attack Assessment Against Differential Fault Analysis,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022.
  78. N. Jessurun, J. Harrison, M. Tehranipoor, and N. Asadi, “PinPoint: An SMD Pin Localization Method” IEEE International Symposium pn Physical and Failure Analysis (IPFA), 2022.
  79. K. Zamiri Azar, H. Kamali, F. Farahmandi, and M. Tehranipoor, “Warm Up before Circuit De-obfuscatio? An Exploration of Possibilities,” IEEE International Symposium on Hardware-Oritented Security and Trust (HOST), 2022.
  80. R. Muttaki, M. Tehranipoor, and F. Farahmandi, “FTC: A Universal Fault Injection Attack Detection Sensor,” IEEE International Symposium on Hardware-Oritented Security and Trust (HOST), 2022
  81. N. Pundir, L. Lin, N. Chang, F. Farahmandi, and M. Tehranipoor, “Security Property Driven Pre-Silicon Laser Fault Injection Assessment,” IEEE International Symposium on Hardware-Oritented Security and Trust (HOST), 2022.
  82. S. Rahman, R. Guo, H. M. Kamali, F. Rahman, F. Farahmandi, M. Abdel-Moneum, and M. Tehranipoor, “O’Clock: Lock the Clock via Clock-gating for SoC IP Protection,” Design Automation Conference (DAC), 2022.
  83. R. Kibria, N. Farzana, F. Farahmandi, and M. Tehranipoor, “FSMx: Finite State Machine Extraction from Flattened Netlist with Application to Security,” IEEE VLSI Test Symposium (VTS), 2022.
  84. C. Xi, N. Jessurun, A. Khan, M. Tehranipoor, and N. Asadi, “A Naturally Inherent Tracking Methodology for Secure Packaging Using Geo-Magnetic Signatures,” GomacTech, 2022.
  85. P. Calzada, J. Harrison, P. Chawla, N. Asadi, and M. Tehranipoor, “PCB Trojan Detection using Optical Imaging,” GOMACTech, 2022.
  86. M. Farmani, J. Harrison, F. Rahman, and M. Tehranipoor, “Efficient Rowhammer-Aware DRAM Test Under Reduced Voltage and Increased Temperature,” GOMACTech, 2022.
  87. M. Azhagan, M. Y. Vutukuru, O. Paradis, M. Tehranipoor, N. Asadi, “Logo Detection and Localization for IC Authentication, Marking Recognition, and Counterfeit Detection,” GOMACTech, 2022.
  88. N. Vashishta, Al Hassan, Md. Mahfuz, F. Rahman, N. Asadi, and M. Tehranipoor, “Trust Validation of Chiplets using a Physical Inspection Based Certificate Authorithy,” Electronic Components and Technology Conference (ECTC), 2022.
  89. D. Mehta, N. Mondol, F. Farahmandi, and M. Tehranipoor, “AIME: Watermarking AL Models by Leveraging Errors,” Design, Automation, and Test in Europe (DATE), 2022.
  90. T. Zhang, F. Rahman, M. Tehranipoor, and F. Farahmandi, “FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain with Blockchain Technology,” IEEE Workshop on Silicon Lifecycle Management (SLM), Oct. 2021.
  91. H. Wang, H. Li, F. Rahman, F. Farahmandi, and M. Tehranipoor, “Security Property-Driven Fault-Injection Vulnerability Assessment of Modern SoCs,” iSecCon, 2021.
  92. S. U. Sami, F. Rahman, D. Donchin, A. Cron, M. Borza, F. Farahmandi, and M. Tehranipoor, “POCA: First Power-on Chip Authentication in Untrusted Foundry and Assembly,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2021.
  93. S. Rahman, H. Li, R. Guo, F. Rahman, F. Farahmandi, and M. Tehranipoor, “LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment,” International Test Conference (ITC), 2021.
  94. A. Vafaei, N. Hooten, M. Tehranipoor, and F. Farahmandi, “Symba: Symbolic Execution at C-level for Hardware Trojan Detection,” International Test Conference (ITC), 2021.
  95. B. Ahmed, F. Rahman, N. Hooten, F. Farahmandi, and M. Tehranipoor, “AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow,” International Conference on Computer-Aided Design (ICCAD), 2021.
  96. N. Pundir, S. Shi, M. Tehranipoor, and F. Farahmandi, “HLS-Induced Information Leakage Verification,” SRC TECHCON, 2021.
  97. J. True, N. Jessurun, D. Mehta, M. Tehranipoor, N. Asadizanjani, “Q.U.A.I.N.T.P.E.A.X. QUantifying Algorithmically INTrinsic Properties of Electronic Assemblies via X-ray CT“, Microscopy and Microanalysis (M&M), August 2021.
  98. J. True, C. Xi, N. Jessurun, K. Ahi, M. Tehranipoor, N. Asadizanjani, “Terahertz Based Machine Learning Approach to Integrated Circuit Assurance” Electronic Components and Technology Conference (ECTC), June 2021
  99. M. M. Al Hasan, N. Vashistha, S. Taheri, M. Tehranipoor, N. Asadizanjani “Generative Adversarial Network for Integrated Circuits Physical Assurance Using Scanning Electron Microscopy“, IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), September 2021.
  100. N. Pundir, F. Farahmandi, and M. Tehranipoor, “HLS-Induced Information Leakage Verification,” TECHCON 2021.
  101. M. M. Rahman, S. Mohammad, J. Vosatka, J. Allen, M. Allen, F. Farahmandi, F. Rahman, and M. Tehranipoor, “HEXON: Protecting Firmware Using Hardware-Assisted Execution-Level Obfuscation,” International Symposium on VLSI (ISVLSI), 2021.
  102. T. Farheen, U. Boreto, N. Varshney, H. Shen, D. Woodard, M. Tehranipoor, and D. Forte, “Proof of Reverse Engineering Barrier: SEM Image Analysis on Covert Gates,” International Sympoium on Test and Failure Analysis (ISTFA), 2021.
  103. S. Aftabjahani, R. Kastner, M. Tehranipoor, F. Farahmandi, J. Oberg, A. Nordstrom, N. Fern, A. Alric, “CAD for Hardware Security – Automation is Key to Adoption of Solution,” IEEE VLSI Test Symposium (VTS), 2021.
  104. H. Wang, F. Farahmandi, and M. Tehranipoor, “SOFI: Security Property-Driven Vulnerability Assessment of ICs Against Fault-Injection Attacks,” SNUG, 2021.
  105. Md. S. Ul Islam, F. Rahman, Farimah Farahmandi, A. Cron, M. Borza, and Mark Tehranipoor, “End-to-End Secure SoC Lifecycle Management,” Design Automation Conference (DAC), 2021.
  106. T. Zhang, J. Park, M. Tehranipoor, and F. Farahmandi, “PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation,” Design Automation Conference (DAC), 2021.
  107. R. Muttaki, M. Tehranipoor, and F. Farahmandi, “HLock: Locking IPs at the High-Level Language,” Design Automation Conference (DAC), 2021.
  108. M. Farmani, F. Rahman, and M. Tehranipoor, “RHAT: Efficient RowHammer-Aware Test for Modern DRAM Modules,” IEEE European Test Symposium (ETS), 2021.
  109. N. Dipu, A. Ayalasomayajula, F. Rahman, F. Farahmandi, and M. Tehranipoor, “SAIF: Automated Asset Identification for Security Verification ar the Register Transfer Level,” IEEE VLSI Test Symposium (VTS), 2021.
  110. J. Harrison, P. Calzada, N. Asadi, and Mark Tehranipoor, “A Comprehensive Benchmark Suite for PCB Assurance,” GoamcTech 2021.
  111. A. Khan, C. Xi, N. Asadi, and Mark Tehranipoor, “Security Assessment of Interposer in Advanced Packaging,” GomacTech 2021.
  112. H. Wang, H. Li, F. Farahmandi, and Mark Tehranipoor, “SOFI: Security Property-Driven Vulnerability Assessment of ICs Against Fault-Injection Attacks,” GoamcTech 2021.
  113. O. Paradis, D. Woodard, M. Tehranipoor, and N. Asadi, “Frameowrk for Automatic OCB Marking Detection and Recognition for Hardware Assurance,” GOMACTech 2021.
  114. N, Jessurrun, O. Paradis, M. Tehranipoor, N. Asadi, “Improvements on the SHADE Algorithm for PCB Component Estimate Refinement,” GOMACTech 2021.
  115. N. Pundir, F. Farahmandi, and M. Tehranipoor, “Secure High-Level Synthesis: Challenges and Solutions,” International Symposium on Quality Electronics Design (ISQED), 2021.
  116. M. M. Hossain, F. Farahmandi, M. Tehranipoor and F. Rahman, “BOFT: Exploitable Buffer Overflow Detection by Information Flow Tracking,” Design, Automation, and Test in Europe (DATE), 2021.
  117. L. Lavdas, M. T. Rahman, M. Tehranipoor, and N. Asadi, “On Optical Attacks Making Logic Obfuscation Fragile,” International Test Conference, Asia (ITC-Asia), 2020..
  118. 2. A. Stern, D. Mehta, S. Tajik, F. Farahmandi, and M. Tehranipoor,, “SPARTA: A Laser Probing Approach for Trojan Detection,” International Test Conference (ITC), 2020.
  119. A. Stern, D. Mehta, S. Tajik, U. Guin, F. Farahmandi, and M. Tehranipoor, “Trust Assessment for Electronic Components using Laster and Emission-based Microscopy,” IEEE RAPID, 2020.
  120. J. Vosatka, A. Stern, M. Hossain, F. Rahman, J. Allen, M. Allen, F. Farahmandi, and M. Tehranipoor, “Confidence Modeling and Tracking of Recycled Integrated Circuits, Enabled by Blockchain,” IEEE RAPID, 2020.
  121. H. Lu, N. Vashishta, N. Asadi, M. Tehranipoor, D. Woodard, “Knowledge-based Object Localization in Scanning Electron Microscopy Images for Hardware Assurance,” International Symposium on Test and Failure Analysis (ISTFA), 2020.
  122. O. Paradis, N. Jessurun, M. Tehranipoor, and N. Asadi, “Color Normalization for Robust Automatic Bill of Materials Generation and Visual Inspection of PCBs,” International Symposium on Test and Failure Analysis (ISTFA), 2020.
  123. N. Jessurun, O. Paradis, M. Tehranipoor, and N. Asadi, “SHADE: Automated Refinement of PCB Component Estimates Using Detected Shadows,” IEEE Conference on Physical Assurance and Inspection of Electronics (PAINE), 2020. (Received Best Student Paper Award)
  124. J. Vosatka, A. Stern, M. M. Hossain, F. Rahman, F. Allen, M. Allen, F. Farahmandi, and M. Tehranipoor, “Tracking Cloned Elecronic Components using a Consortium-based Blockchain Infrastructure,” IEEE Conference on Physical Assurance and Inspection of Electronics (PAINE), 2020.
  125. A. Stern, D. Mehta, S. Tajik, U. Guin, F. Farahmandi, and M. Tehranipoor, “SPARTA: Laser Probing Approach for Sequential Trojan Detection in COTS Integrated Circuits,” IEEE Conference on Physical Assurance and Inspection of Electronics (PAINE), 2020.
  126. A. Duncan, A. Nahiyan, F. Rahman, G. Skipper, M. Swany, A. Lukefahr, F. Farahmandi, and M. Tehranipoor,, “SERFI: Secure Remote FPGA Initialization in an Untrusted Environment,” IEEE VLSI Test Symposium (VTS), 2020.
  127. N. Pundir, F. Rahman, M. Tehranipoor, and F. Farahmandi, “Analyzing Security Vulnerabilities Induced by High-Level Synthesis,” GomacTech 2020.
  128. J. Vosatka, M.M. Hossain, F. Rahman, J. Allen, M. Allen, F. Farahmandi, and M. Tehranipoor, “Modeling Risk in Electronics Supply Chains Enabled by Blockchain,” GomacTech 2020.
  129. A. Stern, A. Duncan, S. Tajik, F. Farahmandi, and M. Tehranipoor, “Sequential Hardware Trojan Detection usong Clock Activity Analysis,” GomacTech, 2020.
  130. A. Duncan, A. Nahiyan, F. Rahman, G. Skipper. M. Swany, A. Lukefahr, F. Farahmandi, and M. Tehranipoor, “SERFI: Secure Remote FPGA Initialization,” GomacTech, 2020.
  131. T. Rahman, S. M. Rahman, S. Tajik, M. Tehranipoor, and N. Asadi, “The Key is Left under the Mat: On the Inappropriate Security Assumption of Logic Locking Schemes,” IEEE International Hardware-Oriented Security and Trust (HOST), 2020.
  132. N. Farzana, F. Rahman, M. Tehranipoor, and F. Farahmandi, “Security Verification of System on Chip using Property Checking,” International Test Conference (ITC), 2019.
  133. A. Duncan, F. Rahman, A. Lukefahr, F. Farahmandi, and M. Tehranipoor, “FPGA Bitstream Security: A Day in the Life,” International Test Conference (ITC), 2019.
  134. M. Azhagan, D. Mehta, H. Lu, S. Agrawal, P. Chawla, M. Tehranipoor, D. Woodard, and Navid Asadi, “A New Framework for Automated Bill of Material Generation and Visual Inspection,” International Symposium on Test and Failure Analysis (ISTFA), 2019.
  135. M. Alam, F. Ganji, S. Tajik, M. Tehranipoor, and D. Forte, “RAM-Jam: Remote Temperature and Voltage Fault Attack on FPGAs using Memory Collisions,” Fault Diagnosis and Tolerance in Cryptography (FDTC), 2019.
  136. F. Ganji, S. Tajik, J. P. Seifert, M. Tehranipoor, and D. Forte, “Approaches for Hardness Amplification of PUFs,” PROOFS, 2019.
  137. J. Park, S. Cho, T. Lim, S. Bhunia, M. Tehranipoor, “SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number Generator,” International Conference on Computer-Aided Design (ICCAD), 2019.
  138. T. Aravin, H. Shen, M. Tehranipoor, and Q. Qu, “LPN-based Device Authentication Using Resistive Memory,” ACM GLS-VLSI, 2019.
  139. A. Duncan, A. Skipper, A, Stern, F. Rahman, A. Nahiyan, A. Lukefahr, M. Swany, and M. Tehranipoor, “FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection,” IEEE International Hardware-Oriented Security and Trust (HOST), 2019.
  140. X. Guo, M. Tehranipoor, and Y. Jin, “QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment,” IEEE International Hardware-Oriented Security and Trust (HOST), 2019.
  141. B. Park, M. Tehranipoor, D. Forte, and N. Maghari, “A Metal-Via Resistance Based Physically Unclonable Function with 1.18% Native Instability,”IEEE Custom Integrated Circuits Conference (CICC), 2019.
  142. J. Park, T. Miao, A. Nahiyan, A. Vassilev, Y. Jin, and M. Tehranipoor, “RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level,” IEEE VLSI Test Symposium (VTS), 2019.
  143. A. Stern, K. Yang, J. Vosatka, A. Duncan, J. Park, D. Forte, and M. Tehranipoor, “RASC: Enabling Remote Access to Side-Channels for Mission Critical Systems,” GomacTech, 2019.
  144. A. Duncan, A. Lukefahr, A. Sterm, M. Tehranipoor, and M. Swany, “Lifetime Physical Authentication of FPGAs Through Infrared Watermarking,” GomacTech, 2019.
  145. Q. Shi, H. Wang, N. Asadi, M. Tehranipoor, and D. Forte, “A Comprehensive Analysis on Vulnerability of Active Shields to Tilted Microprobing Attacks,” IEEE Asian HOST, 2018.
  146. M. T. Rahman, Q. Shi. S. Tajik, H. Shen, D. Woodard, M. Tehranipoor, and N. Asadi, “Physical Inspection and Attacks: New Frontier in Hardware Security,” IEEE International Verification and Security Workshop (IVSW), 2018.
  147. A. Stern, U. Botero, B. Shakya, H. Shen, and M. Tehranipoor, “EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked ICs,” International Test Conference (ITC), 2018.
  148. Y. Han, X. Wang, and M. Tehranipoor, “IPA: Concurrent IC and PCB Authentication Using On-Chip Ring Oscillator Array,” IEEE Asian Test Symposium (ATS), 2018.
  149. H. Shen, N. Asadi, M. Tehranipoor, and D. Forte, “Nanopyramid: An Optical Scrambler Against Backside Probing Attacks,” International Symposium on Test and Failure Analysis (ISTFA), 2018.
  150. H. Shen, M. Tehranipoor, and S. Bhunia, “Tampering, Snooping, and Electromagnetic Attack Proof Coating on Printed Circuit Boards,” International Symposium on Test and Failure Analysis (ISTFA), 2018.
  151. N. Vashistha, H. Shen, T. Rahman, D. Woodard, N. Asadi, and M. Tehranipoor, “Trojan Scanner: Detecting Hardware Trojans with Rapid Imaging Combined with Image Processing and Machine Learning,” International Symposium on Test and Failure Analysis (ISTFA), 2018.
  152. H. Wang, Q. Shi, D. Forte, and M. Tehranipoor, “Metrics and Physical Design Flow for Internal Shielding Against Front Side Probing Attack,” SRC TECHCON, 2018.
  153. A. Nahiyan, D. Forte, and M. Tehranipoor, “Framework for Automated and Systematic Security Assessment of Modern SoCs,” SRC TECHCON, 2018.
  154. K. Yang, J. Park, M. Tehranipoor, and S. Bhunia, “Robust Timing Attack Countermeasure on Virtual Hardware,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018.
  155. J. Park, X. Xu, Y. Jin, D. Forte, and M. Tehranipoor, “Power-based Side-channel Instruction-level Disassembler,” Design Automation Conference (DAC). 2018.
  156. M. Alam, S. Chowdhury, M. Tehranipoor, and U. Guin, “Robust, Low-Cost, and Accurate Detection of Recycled ICs using Digital Signatures,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018.
  157. K. Yang, J. Park, M. Tehranipoor, and S. Bhunia, “Hardware Virtualization for Protection against Power Analysis Attack,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2018.
  158. O. Arias, F. Rahman, M. Tehranipoor, and Y. Jin, “Device Attestation: Past, Present, and Future,” Design Automation, and Test in Europe (DATE), 2018.
  159. E. Principe, N. Asadi, D. Forte, M. Tehranipoor, R. Chivas, M. DiBattista, S. Silverman, M. Marsh, N. Piche, J. Mastovich, “Steps Toward Computational Guided Deprocessing of Integrated Circuits,” GomacTech, 2018.
  160. D. Capecci, D. Forte, M. Tehranipoor, and S. Bhunia, “Automated SoC Security from Design to Fabrication,” GomacTech, 2018.
  161. S. Beireddy, N. Asadi, M. Tehranipoor, D. Woodard, and D. Forte, “Automated Detection of Counterfeit IC Defects Using Image Processing,” GomacTech, 2018.
  162. J. He, X. Guo, M. Tehranipoor, and Y. Jin, “Golden Chip Free Electromagnetic Simulation and Statistical Analysis for Hardware Security,” GomacTech, 2018.
  163. U. Botero, M. Tehranipoor, and D. Forte, “Downgrade: A Framework for Obsolescence Handling through Backwards Compatibility,” GomacTech, 2018.
  164. F. Rahman, M. Farmani, M.Tehranipoor, and Y. Jin, “Hardware-assisted Cybersecurity for IoT Devices,” IEEE Microprocessor Test, Security, and Verification Conference (MTV), 2017.
  165. X. Wang, L. Yu, F. Rahman, and M. Tehranipoor, “IV-PUF: Interconnect Variations PUF with Self-Masking Circuit for Performance Enhancement,” IEEE Microprocessor Test, Security, and Verification Conference (MTV), 2017.
  166. S. Choudhury, X. Xu, M. Tehranipoor, and D. Forte, “Aging-Resistant RO PUF with Increased Reliability in FPGA,” Int. Conference on Reconfigurable Computing and FPGAs (Reconfig), 2017.
  167. A. Chhotaray, A. Nahiyan, T. Shrimpton, D. Forte, and Mark Tehranipoor, “Standardizing Bad Cryptographic Practice – A teardown of the IEEE standard for protecting electronic-design intellectual property,” ACM Conference on Computer and Communication Security (CCS), 2017.
  168. X. Wang, Y. Guo, T. Rahman, D. Zhang, and M. Tehranipoor, “DOST: Dynamically Obfuscated Wrapper for Split Test against IC Piracy,” IEEE Asian Hardware-Oriented Security and Trust Symposium (AsianHOST), 2017. Received Best Paper Award
  169. Z. Guo, X. Xu, M. Tehranipoor, and D. Forte, “MPA: Model-assisted PCB Attestation via Board-level RO and Temperature Compensation,” IEEE Asian Hardware-Oriented Security and Trust Symposium (AsianHOST), 2017.
  170. K. Yang, H. Shen, D. Forte, and M. Tehranipoor, “A Split Manufacturing Approach for Unclonable Chipless RFIDs for Pharmaceutical Supply Chain Security,” IEEE Asian Hardware-Oriented Security and Trust Symposium (AsianHOST), 2017.
  171. E.L. Principe, N. Asadizanjani, D. Forte, M. Tehranipoor, R. Chivas, M. DiBattista, S. Silverman, M. Marsh, J. Mastovich, J. Odum, “Steps Towards Automated Deprocessing of Integrated Circuits,” International Symposium on Test and Failure Analysis (ISTFA), 2017. Received Outstanding Paper Award
  172. A. Nahiyan, M. Sadi, R. Vittal, G. Contreras, D. Forte, and M. Tehranipoor, “Hardware Trojan Detection Through Information Flow Security Verification,” International Test Conference (ITC), 2017.
  173. X. Xu, B. Shakiya, M. Tehranipoor, and D. Forte, “Novel Bypass Attack and BDD-based Tradeoff Analysis Against all Known Logic Locking Attacks,” Conference on Cryptographic Hardware and Embedded Systems (CHES), 2017.
  174. Z. Guo, M. Tehranipoor, and D. Forte, “Memory-based Counterfeit IC Detection Framework,” SRC TECHCON, 2017.
  175. A. Nahiyan, D. Forte, and M. Tehranipoor, “Framework for Automated and Systematic Security Assessment of Modern SoCs,” SRC TECHCON, 2017.
  176. J. Park, M. Corba, A. E. de la Serna, R. Vigeant, M. Tehranipoor, and S. Bhunia, “ATAVE: A Framework for Automatic Timing Attack Vulnerability Evaluation,” IEEE Mid-West Symposium on Circuits and Systems (MWSCAS), 2017.
  177. S. Amir, B. Shakya, D. Forte, M. Tehranipoor, and S. Bhunia, “Comparative Analysis of Hardware Obfuscation for IP Protection,” ACM Great Lake Symposium on VLSI (GLS-VLSI), 2017.
  178. Q. Shi, K. Xiao, D. Forte, and M. Tehranipoor, “Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-Authentication,” ACM Great Lake Symposium on VLSI (GLS-VLSI), 2017.
  179. M. Sadi, S. Kannan, and M. Tehranipoor, “Design of a Digital IP for 3D-IC Die-to-Die Clock Synchronization,” IEEE International Symposium on Circuits & Systems (ISCAS), 2017.
  180. Z. Guo, M. Tehranipoor, and D. Forte, “FFD: A Framework for Fake Flash Detection,” Design Automation Conference (DAC), 2017.
  181. T. Bryant, S. Chowdhury, D. Forte, M. Tehranipoor and N. Maghari, “A Stochastic All-Digital Weak Physically Unclonable Function for Analog/Mixed-Signal Applications,” IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST), 2017.
  182. N. Karimian, M. Tehranipoor, and D. Forte, “Non-Fiducial PPG-based Authentication for Healthcare Application,” Engineering in Medicine and Biology Conference (EMBC), 2017.
  183. N. Karimian, M. Tehranipoor, and D. Forte, “Noise Assessment Framework for Optimizing ECG Key Generation,” International Conference on Technologies for Homeland Security, 2017.
  184. D. Zhang, X. Wang, T. He, and M. Tehranipoor, “A Novel Dynamic Obfuscation Scan Design for Protecting IPs against Scan-Based Attack,” IEEE VLSI Test Symposium (VTS), 2017.
  185. Q. Shi, N. Asadi, D. Forte, and M. Tehranipoor, “Layout-based Microprobing Vulnerability Assessment for Security Critical Applications,” GOMACTech, 2017.
  186. N. Kariminan, Z. Guo, M. Tehranipoor, and D. Forte, “Human Recognition from Photoplethysmography (PPG) Based on Non-fiducial Features,” IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2017.
  187. G. K. Contreras, A. Nahiyan, S. Bhunia, D. Forte, M. Tehranipoor, “Security Vulnerability Analysis of Design-for-Test Exploits for Asset Protection in SoCs,” Asia and South Pacific Design Automation Conference (ASP-DAC), 2017.
  188. R. Karam, T. Hoque, S. Ray, M. Tehranipoor, S. Bhunia, “MUTARCH: Architectural Diversity for FPGA Device and IP Security,” Asia and South Pacific Design Automation Conference (ASP-DAC), 2017.
  189. Z. Guo, M. Tehranipoor, and D. Forte, “Aging Attacks for Key Extraction on Permutation-Based Obfuscation,” IEEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 2016.
  190. T. Rahman, D. Forte, X. Wang, and M. Tehranipoor, “Enhancing Noise Sensitivity of Embedded SRAMs for Robust True Random Number Generation in SoCs,” IEEEE Asian Hardware-Oriented Security and Trust (AsianHOST), 2016.
  191. R. Karam, T. Hoque, S. Ray, M. Tehranipoor and S. Bhunia, “Robust Bitstream Protection in FPGA-based Systems through Low-Overhead Obfuscation,” ReConFig, 2016.
  192. M. Sadi, G. Contreras, D. Tran, J. Chen, L. Winemberg, and M. Tehranipoor, “BIST-RM: BIST-Assisted Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning,” International Test Conference (ITC), 2016.
  193. M. Alam, M. Tehranipoor, and D. Forte, “Recycled FPGA Detection using Exclusive LUT Path Delay Characterization,” International Test Conference (ITC), 2016.
  194. T. Bryant, S. Chowdhury, D. Forte, M. Tehranipoor, and N. Maghari, “A Stochastic Approach to Analog Physical Unclonable Function,” IEEE Midwest Symposium on Circuits and Systems (MWSCAS), 2016.
  195. B. Shakya, N. Asadi, D. Forte, and M. Tehranipoor, “Chip Editor: leveraging Circuit Edit for Logic Obfuscation and Trusted Fabrication,” IEEE International Conference on Computer-Aided Design (ICCAD), 2016.
  196. N. Karimian, D. Woodard, M. Tehranipoor, and D. Forte, “Biometrics for Authentication in Resource-Constrained Systems,” Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2016.
  197. G. Contreras and M. Tehranipoor, “Fault Deterministic Vector Analysis and Seed Extraction for LBIST,” SRC TECHCON, 2016. Received Best in Session Award
  198. M. He and M. Tehranipoor, “Test-Point Insertion Efficiency Analysis for LBIST Applications,” SRC TECHCON, 2016.
  199. M. Sadi and M. Tehranipoor, “BIST-Assisted In-field Aging Reliability Management of SoCs Using On-Chip Clock Sweeping and Machine Learning,” SRC TECHCON, 2016. Received Best in Session Award
  200. T. Rahman, D. Forte, and M. Tehranipoor, “SRAM Inspired Design and Optimization for Developing Robust Security Primitives,” SRC TECHCON, 2016. Received Best in Session Award
  201. N. Asadizanjani, D. Forte, and M. Tehranipoor, “Non-destructive Bond Pull and Ball Shear Failure Analysis Based on Real Structural Properties,” Int. Symposium on Testing and Failure Analysis (ISTFA), 2016.
  202. N. Asadizanjani, H. Chen, B. Shakya, D. Forte, S. Bhunia, and M. Tehranipoor, “A New Methodology to Protect PCBs from Non-destructive Reverse Engineering,” Int. Symposium on Testing and Failure Analysis (ISTFA), 2016.
  203. N. Asadizanjani, S. Gattigowda, N. Dunn, D. Forte, and M. Tehranipoor, “A Database for Counterfeit Electronics and Automatic Defect Detection Based on Image processing and Machine Learning,” Int. Symposium on Testing and Failure Analysis (ISTFA), 2016.
  204. S. Ray, S. Bhunia, Y. Jin, and M. Tehranipoor, “[Extended Abstract] Security Validation in IoT Space,” IEEE VLSI Test Symposium (VTS), 2016.
  205. H. Shen, F. Rahman, B. Shakya, M. Tehranipoor, and D. Forte, “Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs),” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
  206. T. Li, J. Di, M. Tehranipoor, D. Forte, and L. Wang, “Tracking Data Flow at Gate-Level through Structural Checking,” ACM Great Lake Symposium on VLSI (GLSVLSI), 2016.
  207. A. Zaghi and Mark Tehranipoor, “Major Observations from a Specialized REU Program for Engineering Students with ADHD,” American Society for Engineering Education (ASEE), 2016.
  208. F. Rahman, D. Forte, and Mark Tehranipoor, “Reliability vs. Security: Challenges and Opportunities for Developing Reliable and Secure Integrated Circuits,” International Reliability Physics Symposium (IRPS), 2016.
  209. M. Sadi and M. Tehranipoor, “BIST-Assisted Reliability Management of SoC Using On-chip Clock Sweeping and Machine Learning,” IEEE Reliability Innovations Conference (IRIC), 2016 (extended abstract).
  210. K. Yang, D. Forte, and M. Tehranipoor, “UCR: An Unclonable Chipless RFID Tag,” IEEE Symposium on Hardware-Oriented Security and Trust (HOST), 2016. Received Best Paper Candidate
  211. Q. Shi, N. Asadi, D. Forte, and M. Tehranipoor, “A Layout-driven Framework to Assess Vulnerability of ICs to Microprobing Attacks,” IEEE Symposium on Hardware-Oriented Security and Trust (HOST), 2016. Received Best Paper Award
  212. Z. Guo, T. Rahman, M. Tehranipoor, and D. Forte, “A Zero-cost Approach to Detect Recycled SoC Chips Using Embedded SRAM,” IEEE Symposium on Hardware-Oriented Security and Trust (HOST), 2016.
  213. A. Nahiyan, K. Xiao, D. Forte, Y. Jin, and M. Tehranipoor, “AVFSM: A Framework for Identifying and Mitigating Vulnerabilities in FSMs,” Design Automation Conference (DAC), 2016.
  214. Z. Guo, N. Karimian, M. Tehranipoor, and D. Forte, “Hardware Security Meets Biometrics for the Age of IoT,” Int. Symposium on Circuits and Systems (ISCAS), 2016.
  215. T. Meade, Y. Jin, M. Tehranipoor, S. Zhang, “Gate-Level Netlist Reverse Engineering for Hardware Security: Control Logic Register Identification,” Int. Symposium on Circuits and Systems (ISCAS), 2016.
  216. L. Yu, X. Wang, P. Jiao, A. Chen, D. Su, L. Winemberg, M. Sadi, and M. Tehranipoor, “An Efficient All-Digital Alarmer for DVFS-based SOC,” Int. Symposium on Circuits and Systems (ISCAS), 2016.
  217. L. Wu, X. Wang, D. Su, A. Chen, Q. Shi, and M. Tehranipoor, “AES Design Improvement Toward Information Safety,” Int. Symposium on Circuits and Systems (ISCAS), 2016.
  218. M. He, G. Contreras, M. Tehranipoor, D. Tran, and L. Winemberg, “Test Point Insertion Efficiency Analysis for LBIST Applications,” IEEE VLSI Test Symposium (VTS), 2016.
  219. T. Meade, S. Zhang, M. Tehranipoor, and Y. Jin, “A Comprehensive Netlist Reverse Engineering Toolset for IC Trust,” GomacTech, 2016.
  220. N. Asadi, S. Shahbazi, D. Forte, and M. Tehranipoor, “Nondestructive X-ray Tomography Based Bond Pull and Ball Shear Analysis,” GomacTech, 2016.
  221. Z. Guo, N. Karimian, M. Tehranipoor, and D. Forte, “Biometric Based Human-to-Device (H2D) Authentication,” GomacTech, 2016.
  222. M. Alam, N. Asadi, S. Shahbazi, D. Forte, and M. Tehranipoor, “The Impact of X-ray Tomography on the Reliability of FPGAs,” GomacTech, 2016.
  223. B. Shakya, F. Rahman, M. Tehranipoor, and D. Forte, “Security in Nanoscale Regime – A Perspective Paper,”IEEE Microprocessor Test and Verification (MTV), 2015.
  224. K. Ahi, N. Asadi, M. Tehranipoor, and M. Anwar, “Authentication of electronic components by time domain THz Techniques,”Connecticut Microelectronic Symposium (CMOC), 2015 (extended abstract).
  225. K. Yang, D. Forte, and M. Tehranipoor, “Protecting Endpoint Devices in IoT Supply Chain,”International Conference on Computer-Aided Design (ICCAD), 2015.
  226. . Shi, R. Tekumalla, and M. Tehranipoor, “Concurrent Testing of Logic and Memory, and Detection of Memory Functional Paths in SOCs,”International Test Conference, 2015 (inivted), 2015.
  227. B. Shakya, U. Guin, M. Tehranipoor, and D. Forte, “Performance Optimization for On-Chip Sensors to Detect Recycled ICs,”IEEE Int. Conference on Computer Design (ICCD), 2015.
  228. T. Rahman, F. Rahman, D. Forte, and M. Tehranipoor, “A Pair Selection Algorithm for Robust RO-PUF Against Environmental Variations and Aging,”IEEE Int. Conference on Computer Design (ICCD), 2015.
  229. G. Contreras, L. Winemberg, M. Tehranipoor, and N. Ahmed, “Predictive LBIST Model and partial ATPG for Seed Extraction,”IEEE Defect and Fault Tolerant Systems (DFTS), 2015.
  230. S. Chen, J. Chen, D. Forte, J. Di, M. Tehranipoor, and L. Wang, “Chip Level Anti-reverse Engineering using Transformable Interconnects,”IEEE Defect and Fault Tolerant Systems (DFTS), 2015.
  231. N. Asadi, S. Shahbaz, M. Tehranipoor, and D. Forte, “Non-destructive PCB Reverse Engineering Using X-ray Micro Computed Tomography,”Int. Symposium for Testing and Failure Analysis (ISTFA), 2015.
  232. H. Dogan, M. Mahbub, N. Asadi, S. Shahbaz, D. Forte, and M. Tehranipoor, “Analyzing the Impact of X-ray Tomography for Non-destructive Counterfeit Detection,”Int. Symposium for Testing and Failure Analysis (ISTFA), 2015.
  233. K. Ahi, N. Asadi, S. Shahbaz, M. Tehranipoor, and M. Anwar, “Terahertz Characterization of Electronic Components and Comparison of Terahertz Imaging with X-ray Imaging Techniques,”Terahertz Physics, Devices, and Systems, 2015.
  234. K. Yang, D. Forte, and M. Tehranipoor, “ReSC: RFID-enabled Supply Chain Management and Traceability for Network Devices,”RFID Security, 2015.
  235. T. Rahman, D. Forte, and M. Tehranipoor, “Robust SRAM-PUF: Cell Stability Analysis and Novel Bit-Selection Algorithm,”TECHCON, 2015.
  236. M. Sadi and M. Tehranipoor, “An Efficient Speed Binning Methodology for SoC Using On-chip Slack Sensors and Machine Learning,”TECHCON, 2015.
  237. J. Chandy, et. al, “Hardware Hacking: An Approach to Trustable Computing Systems Security Education,”The Colloquium for Information Systems Security Education (CISSE), Las Vegas, June 2015.
  238. Z. Guo, J. Di, M. Tehranipoor, and D. Forte, “Investigation of Obfuscation-based Anti-Reverse Engineering for Printed Circuit Boards,”Design Automation Conference (DAC), 2015.
  239. M. Sadi, X. Wang, L. Winemberg, and M. Tehranipoor, “Speed Binning using Machine Learning and On-chip Slack Sensors,”ACM Great Lake Symposium on VLSI (GLSVLSI), 2015.
  240. M. Sadi and M. Tehranipoor, “Timing Slack Extraction for SoC Reliability Monitoring with Robust Digital Sensor IP and Sensor Insertion Flow,”IEEE Reliability Innovations Conference (IRIC), 2015 (extended abstract).
  241. T. Rahman, A. Hosey, K. Xiao, D. Forte, and M. Tehranipoor, “Cell Stability Analysis and Novel Bit-Selection Algorithm for Robust SRAM-PUF,”Connecticut Microelectronic Symposium (CMOC), 2015.
  242. M. Sadi and M. Tehranipoor, “A Robust Multipurpose Digital Sensor IP for In-situ Path Timing Slack Monitoring in SOCs,”IEEE VLSI Test Symposium (VTS), 2015.
  243. K. Xiao, D. Forte, and M. Tehranipoor, “Efficient and Secure Split Manufacturing via Obfuscated Built-In Self-Authentication,”IEEE Hardware-Oriented Security and Trust (HOST), 2015. Received Best Paper Award
  244. K. Yang, D. Forte, and M. Tehranipoor, “An RFID-based Technology for Electronic Component and System Counterfeit Detection and Traceability,”IEEE International Conference on Technologies for Homeland Security (HST), 2015.
  245. G. Contreras, M. Tehranipoor, N. Ahmed, L. Winemberg, and Y. Zhao, “LBIST Pattern Reduction by Learning ATPG Test Cube Properties,”International Symposium on Quality Electronic Design (ISQED), 2015.
  246. S. Quadir, N. Asadi, D. Forte, and M. Tehranipoor, “Rapid Non-destructive Reverse Engineering of Printed Circuit Boards by High Resolution X-ray Tomography,”GOMACTech, 2015.
  247. T. Rahman, A. Hosey, F. Rahman, D. Forte, and M. Tehranipoor, “RePa: A Pair Selection Algorithm for Reliable KeMys from RO-based PUF,”GOMACTech, 2015.
  248. H. Dogan, D. Forte, and M. Tehranipoor, “Aging Analysis for Recycled FPGA Detection,”GOMACTech, 2015.
  249. X. Wang, L. Winemberg, A. Haggag, J. Chayachinda, A. Saluja and M. Tehranipoor, “Fast Aging Degradation Rate Prediction During Production Test,”International Reliability Physics Symposium (IRPS), 2014.
  250. M. Sadi, Z. Conroy, B. Eklow, M. Kamm, N. Bidokhti, and M. Tehranipoor, “An All-Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SOCs,”IEEE Asian Test Symposium (ATS), 2014.
  251. A. Hosey, T. Rahman, K. Xiao, D. Forte, and M. Tehranipoor, “Advanced Analysis of Cell Stability for Reliable SRAM PUFs,”IEEE Asian Test Symposium (ATS), 2014.
  252. H. Dogan, D. Forte, and M. Tehranipoor, “Aging Analysis for Recycled FPGA Detection,”IEEE Int. Symposium on Defect and Fault Tolerance Symposium (DFTS), Oct. 2014.
  253. M. He and M. Tehranipoor, “SAM: A Comprehensive Mechanism for Accessing Embedded Sensors in Modern SoCs,”IEEE Int. Symposium on Defect and Fault Tolerance Symposium (DFTS), Oct. 2014.
  254. T. Rahman, D. Forte, Q. Shi, G. Contreras, and M. Tehranipoor, “CSST: Preventing Distribution of Unlicensed and Rejected ICs by Untrusted Foundry and Assembly,”IEEE Int. Symposium on Defect and Fault Tolerance Symposium (DFTS), Oct. 2014.
  255. M. Sadi and M. Tehranipoor, “A SOC Noise Monitoring and Diagnosis with Fully Digital On-Chip Distributed Sensor Network,”SRC TECHCON, 2014.
  256. G. Contreras and M. Tehranipoor, “Improving LBIST Pattern Quality and Test Point Reduction,”SRC TECHCON, 2014.
  257. Q. Shi, X. Wang, L. Winemberg, and M. Tehranipoor, “On-Chip Sensor Selection for Effective Speed-Binning,”IEEE Mid-West Symposium on Circuits and Systems (MWSCAS), Oct. 2014.
  258. S. Shahbaz, D. Forte, and M. Tehranipoor, “Advanced Physical Inspection Methods for Counterfeit Detection,”Int. Symposium for Testing and Failure Analysis (ISTFA), 2014.
  259. S. Shahbaz, D. Forte, and M. Tehranipoor, “Advanced Physical Inspection Techniques for Counterfeit IC Detection,”Calce Symposium on Counterfeit Electronics and Supply Chain, June 2014.
  260. T. Rahman, D. Forte, Q. Shi, G. Contreras, and M. Tehranipoor, “CSST: An Efficient Secure Split-Test for Preventing IC Piracy,” IEEE North Atlantic Test Workshop (NATW), 2014.
  261. G. Contreras, N. Ahmed, L. Winemberg, and M. Tehranipoor, “TAME-TPI: A Timing-Aware Metric for Efficient Test Point Insertion and Area Overhead Reduction,” IEEE North Atlantic Test Workshop (NATW), 2014.
  262. M. Sadi and M. Tehranipoor, “On-Chip Sensors for Chip Timing Failure Analysis,” Connecticut Symposium on Microelectronics and Optoelectronics (CMOC), 2014.
  263. M. Sadi, Z. Conroy, M. Kamm, B. Eklow, N. Bidokhti and M. Tehranipoor, “System on Chip Noise Reliability Testing and Monitoring with Light-Weight Fully Digital Embedded Sensor Network,” IEEE International Reliability Innovation Conference (IRIC), 2014.
  264. K. Xiao, T. Rahman, D. Forte, M. Tehranipoor, M. Su, and Y. Huang, “Bit Selection Algorithm Suitable for High Volume Production of SRAM PUF,” IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2014.
  265. U. Guin, D. Forte, and M. Tehranipoor, “Low-Cost On-Chip Structures for Combating Die and IC Recycling,” Design Automation Conference (DAC), 2014.
  266. T. Rahman, K. Xiao, D. Forte, X. Zhang, Z. Shi, and M. Tehranipoor, “TI-TRNG: Technology Independent True Random Number Generator,” Design Automation Conference (DAC), 2014.
  267. J. Chen, L. Winemberg, and M. Tehranipoor, “Identification of Testable Representative Paths for Low-Cost Verification of Circuit Performance During Manufacturing Tests and in the Field,” IEEE VLSI Test Symposium (VTS), 2014.
  268. S. Hamdiui, G. Di Natalie, G. van Battum, J. Danger, F. Smailbegovic, and M. Tehranipoor, “Hacking and Protecting IC Hardware,” Design, Automation, and Test in Europe (DATE), 2014.
  269. T. Rahman, D. Forte, M. Tehranipoor, and J. Fahrny, “ARO-PUF: An Aging-Resistant Ring-Oscillator PUF Design,” Design, Automation, and Test in Europe (DATE), 2014.
  270. K. Xiao, T. Rahman, D. Forte, M. Tehranipoor, Y. Huang, and M. Su, “Low-cost Analysis of SRAM PUFs for Identification of Mass-Produced Electronic Devices,” GOMACTech, 2014.
  271. U. Guin, D. Forte, D. DiMase, and M. Tehranipoor, “Counterfeit IC Detection: Test Method Selection Considering Test Time, Cost, and Tiel Level Risk,” GOMACTech, 2014.
  272. U. Guin, D. Forte, and M. Tehranipoor, “Low-cost On-Chip Structures for Combating Die and IC Recycling,” GOMACTech, 2014.
  273. N. Bidokhti, M. Tehranipoor, J. Chen, and J. Lee, “Life After Failure,” Reliability and Maintainability Symposium (RAMS), 2014.
  274. U. Guin, D. Forte, and M. Tehranipoor, “Anti-Counterfeit Techniques: From Design to Resign,” IEEE Microprocessor Test Verification (MTV), 2013.
  275. J. Chen and M. Tehranipoor, “Critical Paths Selection and Test Cost Reduction Considering Process Variations,” IEEE Asian Test Symposium (ATS), 2013.
  276. F. Bao, H. Chen, and M. Tehranipoor, “Worst-case Critical-Path Delay Analysis Considering Power-Supply Noise,” IEEE Asian Test Symposium (ATS), 2013.
  277. A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, and L.T. Wang, “On Achieving Capture Power Safety in At-speed Scan-based Logic BIST,” IEEE Asian Test Symposium (ATS), 2013.
  278. U. Guin and M. Tehranipoor, “CDIR: Low-Cost Combating Die/IC Recycling Structures,” DMSMS, 2013 (Extended Abstract).
  279. U. Guin, D. DiMase, and M. Tehranipoor, “CDIR: Low-Cost Combating Die/IC Recycling Structures,” DMSMS, 2013 (Extended Abstract).
  280. A. Mazady, H. Chi Chou, M. Tehranipoor and M. Anwar, “Terahertz Spectroscopy: A Technology Platform for the Detection of Counterfeit Electronics,” DMSMS, 2013 (Extended Abstract).
  281. U. Guin, T. Chakraborty, and M. Tehranipoor, “Novel DFTs for Circuit Initialization to Reduce Functional Fmax Test Time,” IEEE Int. Conference on Computer Design (ICCD), 2013.
  282. H. Salmani, M. Tehranipoor, and R. Karri, “Trust Benchmarks and Design Vulnerability Analysis,” IEEE Int. Conference on Computer Design (ICCD), 2013.
  283. G. Contreras, T. Rahman, and M. Tehranipoor, “Secure Split-Test for Preventing IC Piracy by Untrusted Foundry and Assembly,” Int. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 2013.
  284. H. Salmani and M. Tehranipoor, “Analyzing Circuit Vulnerability to Hardware Trojan Insertion at the Behavioral Level,” Int. Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), 2013.
  285. Q. Shi, J. Chen, and M. Tehranipoor, “Silicon Data Based Delay Analysis and PDF Pattern Generation for Advanced Technology Node,” SRC TECHCON, September 2013.
  286. M. Tehranipoor, “An All-in-One Anti-Counterfeiting Technology for Integrated Circuits,” Symposium on Counterfeit Electronic Parts and Electronic Supply Chain, June 2013.
  287. Q. Shi, X. Wang, L. Winemberg, and M. Tehranipoor, “Experimental Analysis of Variations’ Impact on Integrated Circuits Performance in Advanced Technology Nodes,” IEEE North Atlantic Test Workshop (NATW), 2013.
  288. U. Guin, T. Chakraborty, and M. Tehranipoor, “Novel DFTs for Circuit Initialization to Reduce Functional Fmax Test Time,” IEEE North Atlantic Test Workshop (NATW), 2013.
  289. U. Guin and M. Tehranipoor, “On Selection of Counterfeit IC Detection Methods,” IEEE North Atlantic Test Workshop (NATW), 2013. Received Best Paper Award
  290. K. X. Zhang, K. Xiao, M. Tehranipoor, J. Rajendran, and R. Karri, “A Study on the Effectiveness of Trojan Detection Techniques using a Red Team Blue Team Approach,” IEEE VLSI Test Symposium (VTS), 2013.
  291. K. Xiao and M. Tehranipoor, “Built-In Self-Authentication for Preventing Hardware Trojan Insertion,” Int. IEEE Symposium on Hardware-Oriented Security and Trust (HOST), 2013.
  292. G. Contreras and M. Tehranipoor, “ATPG Learning BIST for Increasing Pattern Effectiveness,” IEEE International Reliability Innovation Conference (IRIC), 2013.
  293. J. Chen and M. Tehranipoor, “Efficient Skew Reduction for Clock Tree Design Considering NBTI and Process Variation,” IEEE International Reliability Innovation Conference (IRIC), 2013.
  294. M. Tehranipoor and U. Guin, “Counterfeit Detection Technology Assessment,” GOMACTech-2013.
  295. M. Tehranipoor and K. Xiao, “BISA: Built-In Self-Authentication to Prevent Insertion of Trojans by Untrusted Foundry,” GOMACTech-2013.
  296. J. Chen and M. Tehranipoor, “A Novel Flow for Reducing Clock Skew Considering NBTI Effect and Process Variations,” Int. Symposium on Quality Electronics Design (ISQED), 2013.
  297. W. Zhao and M. Tehranipoor, “PowerMAX: Fast Power Analysis During Test,” IEEE Asian Test Symposium (ATS), 2012 (invited).
  298. X. Wang, D. Tran, S. George, L. Winemberg, N. Ahmed, S. Palosh, A. Dobin, and M. Tehranipoor, “Radic: A standard-cell Based Sensor for On-Chip Aging and Flip-Flop Metastability Measurements” Int. Test Conference (ITC), 2012.
  299. X. Wen, Y. Nishida, K. Miyase, S. Kajihara, P. Girard, M. Tehranipoor, and L.T. Wang, “On Pinpoint Capture Power Management in At-Speed Scan Test Generation,” Int. Test Conference (ITC), 2012.
  300. S. Wang, J. Chen, and M. Tehranipoor, “Representative Critical Reliability Paths for Low-Cost and Accurate On-Chip Aging Evaluation,” Int. Conf. on Computer-Aided Design (ICCAD), 2012.
  301. A. Ferraiuolo, X. Zhang, and M. Tehranipoor, “Experimental Analysis of a Ring Oscillator Network for Hardware Trojan Detection in a 90nm ASIC” Int. Conf. on Computer-Aided Design (ICCAD), 2012
  302. X. Zhang, K. Xiao, and M. Tehranipoor, “Path-Delay Fingerprinting for Identification of Recovered ICs” in Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2012. Received Best Student Paper Award
  303. M. Tehranipoor, “SST: Secure Split-Test for Preventing IC Piracy and Easy Detection,” DMSMS & Standardization, 2012.
  304. N. Murphy, U. Guin, and M. Tehranipoor, “Counterfeit Detection Technology Assessment,” DMSMS & Standardization, 2012.
  305. X. Zhang, N. Tuzzio, and M. Tehranipoor, “Identification of Recovered ICs using Fingerprints from a Light-Weight On-Chip Sensor,” IEEE/ACM Design Automation Conference (DAC), 2012.
  306. S. Wang, Q. Shi, J. Chen, and M. Tehranipoor, “On-Chip Structures and Test Methodologies for Analyzing Performance Degradation in Modern Designs,” SRC TECHCON, 2012.
  307. N. Tuzzio, K. Xiao, X. Zhang, and M. Tehranipoor, “A Zero-Overhead IC Identification Technique using Clock Sweeping and Path Delay Analysis” IEEE GLSVLSI, 2012.
  308. S. Wang and M. Tehranipoor, “TSUNAMI: “A Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise during Functional and Test Operations,” IEEE GLSVLSI, 2012.
  309. J. Chen, S. Wang, and M. Tehranipoor, “Efficient Selection and Analysis of Critical Reliability Paths and Gates,” IEEE GLS-VLSI, 2012.
  310. M. Tehranipooor, “Combating IC Recovery for Improving Reliability and Security of Digital Integrated Circuits,” IEEE Int. Reliability Innovations Conference (IRIC), 2012 (Extended Abstract).
  311. M. Tehranipoor, L. Winemberg, and N. Bidokhti, “Timing Analysis and On-Chip Measurement Considering Aging,” IEEE Int. Reliability Innovations Conference (IRIC), 2012 (Extended Abstract).
  312. W. Zhao, S. Chakravarty, J. Ma, N. Devta-Prasanna, F. Yang, M. Tehranipoor, “A Novel Method for Fast Identification of Peak Current during Test,” IEEE VLSI Test Symposium (VTS), 2012.
  313. X. Zhang, N. Tuzzio, and M. Tehranipoor, “CDR: Combating Die Recovery,” GOMACTech, Las Vegas, 2012.
  314. M. Li, A. Davoodi, and M. Tehranipoor, “A sensor-assisted self-authentication framework for hardware Trojan detection“, in Proc. Design, Automation, and Test in Europe (DATE), 2012.
  315. X. Zhang, N. Tuzzio, and M. Tehranipoor, “Red Team: Design of Intelligent Hardware Trojans with Known Defense Schemes,” Int. Conference on Computer Design (ICCD), 2011.
  316. F. Bao, K. Peng, K. Chakrabarty, and M. Tehranipoor, “On Generation of 1-Detect TDF Pattern Set with Significantly Increased SDD Coverage,” IEEE Asian Test Symposium (ATS), 2011.
  317. H. Slamani, M. Tehranipoor, S. Chakravarty, X. Wen, and P. Girard, “Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns,” IEEE LPonTR, 2011.
  318. F. Wu, L. Dilillo, A. Bosio, P. Girard, M. Tehranipoor, K. Miyase, X. Wen, N. Ahmed, “Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme,” IEEE LPonTR, 2011.
  319. J. Chen and M. Tehranipoor, “On-Chip Structures and Methodologies for Reliable Circuit Design,” Psoter, SRC TECHCON, 2011.
  320. S. Wang, L. Winemberg, and M. Tehranipoor, “In-Field Aging Measurement and Calibration for Power-Performance Optimization,” in Proc. Design Automation Conference (DAC), 2011.
  321. W. Zhao and M. Tehranipoor, “Peak Power Identification on Power Bumps During Test Application,” Low Power SOC Workshop (LPSOC), 2011 (Invited).
  322. X. Zhang and M. Tehranipoor, “Case Study: Detecting Hardware Trojans in Third-Party Digital IP Cores,” in Int. IEEE Hardware-Oriented Security and Trust (HOST), 2011.
  323. F. Bao, K. Peng, M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “Critical Fault-Based Pattern Generation for Screening Small Delay Defects,” in proc. European Test Symposium (ETS), 2011.
  324. S. Wang and M. Tehranipoor, “Aging Measurement and Calibration for Nanoscale VLSI Circuit,” Connecticut Symposium on Microelectronics and Optoelectronics (CMOC), 2011 (Invited).
  325. J. Chen and M. Tehranipoor, “Timing Analysis for Nanometer VLSI Designs Considering Aging Effects,” Connecticut Symposium on Microelectronics and Optoelectronics (CMOC), 2011 (Poster).
  326. X. Zhang and M. Tehranipoor, “RON: An On-chip Ring Oscillator Network for Hardware Trojan Detection,” Design, Automation, and Test in Europe (DATE), 2011.
  327. F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, and N. Ahmed, “Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing,” in Design & Technology of Integrated Systems (DTIS), 2011.
  328. W. Zhao, S. Chakravarty, and M. Tehranipoor, “Power-Safe Test Application Using An Effective Gating Approach Considering Current Limits,” IEEE VLSI Test Symposium (VTS), 2011.
  329. K. Peng, F. Bao, G. Shofner, L. Winemberg, and M. Tehranipoor, “Case Study: Efficient SDD Test Generation for Very Large Integrated Circuits,” IEEE VLSI Test Symposium (VTS), 2011
  330. J. Ma, N. Ahmed, and M. Tehranipoor, “Low-Cost Diagnostic Pattern Generation and Evaluation Procedures for Noise-Related Failures,” IEEE VLSI Test Symposium (VTS), 2011.
  331. X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Kajihara, P. Girard, M. Tehranipoor, “Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing,” IEEE VLSI Test Symposium (VTS), 2011.
  332. X. Zhang and M. Tehranipoor, “Verifying Trustworthiness of Integrated Circuits,” GOMACTech, 2011 (Invited).
  333. J. Chen, S. Wang, N. Bidokhti, and M. Tehranipoor, “A Framework for Fast and Accurate Critical-Reliability Paths Identification,” IEEE North Atlantic Test Workshop (NATW), 2011.
  334. F. Bao, K. Peng, K. Chakrabarty, L. Winemberg, and M. Tehranipoor, “Increasing SDD Coverage without Increasing Pattern Count,” IEEE North Atlantic Test Workshop (NATW), 2011.
  335. N. Reddy, S. Wang, L. Winemberg, and M. Tehranipoor, “Experimental Analysis for Aging in Integrated Circuits,” IEEE North Atlantic Test Workshop (NATW), 2011.
  336. J. Ma, M. Tehranipoor, O. Sinanoglu, and S. Almukhaizim, “Identification of IR-drop Hot-spots in Defective Power Distribution Network Using TDF ATPG,” IEEE International Workshop on Design and Test (IDT), Abu Dhabi, 2010.
  337. M. Tehranipoor, “Dealing with Reliability and Variability Issues in Nanometer Technology Designs,” Connecticut Symposium on Microelectronics and Optoelectronics (CMOC), 2010 (Invited).
  338. H. Salmani, M. Tehranipoor, and J. Plusquellic, “A Layout-Aware Approach for Improving Localized Switching to Detect Hardware Trojans in Integrated Circuits,” IEEE International Workshop on Information Forensics and Security (WIFS), 2010.
  339. W. Zhao, J. Ma, M. Tehranipoor, and S. Chakravarty, “Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test,” IEEE Asian Test Symposium (ATS), 2010.
  340. K. Peng, M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection,” IEEE Asian Test Symposium (ATS), 2010.
  341. S. Goel, K. Chakrabarty, M. Yilmaz, K. Peng, and M. Tehranipoor, “Circuit Topology-Based Test Pattern Generation for Small-Delay Defects,” IEEE Asian Test Symposium (ATS), 2010.
  342. F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, K. Miyase, X. Wen, and N. Ahmed, “Power reduction Through X-filling of Transition Fault Vectors for LOS Testing,” International Workshop on the Impact of Low Power design on Test and Reliability (LPonTR), 2010.
  343. K. Peng, Y. Huang, W. T. Cheng, and M. Tehranipoor, “Full-Circuit SPICE Simulation Based Validation of Dynamic Delay Estimation,” European Test Symposium (ETS), 2010.
  344. F. Wu, L. Dilillo, A. Bosio, P. Girard, S. Pravossoudovitch, A. Virazel, M. Tehranipoor, J. Ma, W. Zhao, X. Wen, “Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing Schemes,” DDECS, 2010.
  345. X. Wang and M. Tehranipoor, “Low-Cost On-Chip Structures for Measuring NBTI Effects, Variations, Path Delay, and Noise,” SRC TECHCON, Poster Presentation, 2010. Received Best in Session Award
  346. J. Ma and M. Tehranipoor, “A Low-Cost Diagnostic Procedure for Parametric Failures Caused by Pattern-Induced Noises,” SRC TECHCON, Poster Presentation, 2010.
  347. J. Ma, J. Lee, N. Ahmed, P. Girard, and M. Tehranipoor, “Pattern Grading for Testing Critical Paths Considering Power Supply Noise and Crosstalk Using a Layout-Aware Quality Metric,” in ACM Great-Lake Symposium on VLSI (GLS-VLSI), 2010.
  348. K. Peng, J. Thibodeau, M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “A Novel Hybrid Method for SDD Pattern Grading and Selection,” in IEEE VLSI Test Symposium (VTS), 2010.
  349. X. Wang and M. Tehranipoor, “Novel Physical Unclonable Function Based on Process and Environmental Variations,” in Design, Automation, and Test in Europe (DATE), 2010.
  350. K. Peng, M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “High-Quality Pattern Selection for Screening Small-Delay Defects Considering Process Variations and Crosstalk,” in Design, Automation, and Test in Europe (DATE), 2010.
  351. K. Peng, Y. Huan, R. Guo, W. T. Cheng, and M. Tehranipoor, “Emulating and Diagnosing IR-Drop by Using Dynamic SDF,” in ASP-DAC, 2010.
  352. K. Peng, Y. Huang, W. T. Cheng, and M. Tehranipoor, “Efficient Modeling of IR-Drop Using Dynamic SDF for Test and Diagnosis,” in IEEE Workshop on RTL and High Level Testing (WRTLT), 2009.
  353. X. Wang, M. Tehranipoor, and R. Datta, “A Novel Architecture for On-Chip Path Delay Measurement,” in International Test Conference (ITC), 2009.
  354. J. Ma, J. Lee, and M. Tehranipoor, “Extended Abstract: Developing a Novel Quality Metric for Path-Delay Fault Pattern Evaluation,” in IEEE Int. Workshop on Defect and Data Driven Testing (D3T), 2009.
  355. K. Peng, M. Yilamaz, K. Chakrabarty, and M. Tehranipoor, “Efficient Pattern Grading for Small Delay Defects in Digital Integrated Circuits,” IEEE North Atlantic Test Workshop (NATW), May 2009. Received Best Paper Award
  356. H. Salmani, M. Tehranipoor, and J. Plusquellic, “New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time,” in IEEE Workshop on Hardware-Oriented Security and Trust (HOST), 2009.
  357. J. Ma, J. Lee, and M. Tehranipoor, “Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths,” in Proc. IEEE VLSI Test Symposium (VTS), 2009.
  358. J. Ma, J. Lee, and M. Tehranipoor, “Layout-Aware Pattern Generation for Critical Paths Considering Supply Voltage Noise,” Poster Presentation, SRC TECHCON, Austin, TX, 2009. Received Best in session Award
  359. H. Furukawa, X. Wen, K. Miyase, Y. Yamoto, S. Kajihara, P. Girard, L.T. Wang, M. Tehranipoor, “CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Testing,” in Proc. IEEE Asian Test Symposium (ATS), 2008.
  360. J. Ma, J. Lee, M. Tehranipoor, X. Wen, A. Crouch, “Identification of IR-drop Hot-spots in Defective Power Distribution Network Using TDF ATPG,” in Proc. Int. Workshop on Defect and Data Driven Testing (D3T), 2008.
  361. M. tehranipoor, “ATPG for Increased Test Quality and In-Field Reliability,” DRV Workshop, 2008 (Invited).
  362. X. Wang, M. Tehranipoor, and R. Datta, “Path-RO: A Novel On-Chip Critical Path Delay Measurement Under Process Variations,” in Proc. International Conference on Computer-Aided Design (ICCAD), Nov. 2008.
  363. R. Rad, X. Wang, J. Plusquellic, and M. Tehranipoor, “Taxonomy of Trojans and Methods of Detection for IC Trust,” in Proc. International Conference on Computer-Aided Design (ICCAD), Nov. 2008.
  364. X. Wang, H. Salmani, M. Tehranipoor, and J. Plusquellic, “Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis,” in Proc. International Symposium on Fault and Defect Tolerance in VLSI Systems (DFT), Oct. 2008.
  365. X. Wang, M. Tehranipoor, and R. Datta “Accurate On-Chip Path Delay Measurement,” Texas Instruments Symposium on Test (TIST), Aug. 2008
  366. J. Lee and M. Tehranipoor, “A Novel Test Pattern Generation Framework for Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths,” in Proc. IEEE International Test Conference (ITC), Oct. 2008.
  367. M. Yilmaz, K. Chakrabarty and M. Tehranipoor, “Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects,” in Proc. IEEE International Test Conference (ITC), Oct. 2008.
  368. J. Ma, J. Lee, and M. Tehranipoor, “Power Distribution Failure Analysis Using Transition-Delay Fault Pattern Generation,” Poster presentation at IEEE International Test Conference (ITC), Oct. 2008.
  369. X. Wang, M. Tehranipoor, and R. Datta “Path-RO: On-Chip Critical Path Delay Measurement Under Process Variations,” IEEE North Atlantic Test Workshop (NATW), May 2008. Received Best Paper Award
  370. J. Ma, J. Lee, M. Tehranipoor, and A. Crouch “Test Pattern Generation for Open Defects in Power Distribution Networks,” IEEE North Atlantic Test Workshop (NATW), May 2008.
  371. J. Lee, S. Narayan, and M. Tehranipoor, “Low-Power Transition-Delay Fault Pattern Generation,” IEEE North Atlantic Test Workshop (NATW), May 2008. Received Honorable Mention for Best Paper Award
  372. X. Wang, M. Tehranipoor, and J. Plusquellic, “Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions,” IEEE Int. Hardware-Oriented Security and Trust (HOST), 2008.
  373. R. Rad, J. Plusquellic, and M. Tehranipoor, “Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals,” IEEE Int. Hardware-Oriented Security and Trust (HOST), 2008.
  374. J. Lee and M. Tehranipoor, “LS-TDF: Low Switching Transition Delay Fault Test Pattern Generation,” in Proc. IEEE VLSI Test Symposium (VTS), 2008.
  375. M. Yilmaz, K. Chakrabarty, and M. Tehranipoor, “Test Grading and Pattern Selection for Small Delay Defects,” in Proc. IEEE VLSI Test Symposium (VTS), 2008.
  376. J. Lee, S. Narayan, M. Kapralos, and M. Tehranipoor, “Layout-aware, IR-drop Tolerant Transition Fault Pattern Generation,” in Proc. Design, Automation, and Test in Europe (DATE), 2008.
  377. J. Lee, K. Peng, and M. Tehranipoor, “Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths,” Poster presentation, SRC TECHCON, Austin, TX, 2008.
  378. M. Yilmaz, K. Chakrabarty and M. Tehranipoor, “Test Pattern Grading for Small Delay Defects,” Int. Workshop on Defect-Based Testing (DBT’07), 2007.
  379. R. Helinski, J. Plusquellic and M. Tehranipoor, “Small Delay Defect Detection Using Self-Relative Timing Bounds,” Int. Workshop on Defect-Based Testing (DBT’07), 2007.
  380. J. Lee and M. Tehranipoor, “Delay Fault Testing in Presence of Maximum Crosstalk,” 16th IEEE North Atlantic Test Workshop (NATW’07), Boxborough, MA, 2007.
  381. N. Ahmed, M. Tehranipoor and V. Jayaram, “IR-drop Tolerant Transition Delay Fault Testing,” 16th IEEE North Atlantic Test Workshop (NATW’07), Boxborough, MA, 2007.
  382. N. Ahmed, M. Tehranipoor and V. Jayaram, “Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design,” in Proc. Design Automation Conference (DAC’07), 2007.
  383. N. Ahmed, M. Tehranipoor and V. Jayaram, “Supply Voltage Noise Aware ATPG for Transition Delay Faults,” in Proc. IEEE VLSI Test Symposium (VTS’07), 2007.
  384. N. Ahmed and M. Tehranipoor, “Supply Voltage Noise Aware ATPG for Transition Delay Faults,” TECHCON, Austin, TX 2007.
  385. N. Ahmed, M. Tehranipoor and V. Jayaram, “Improving ATPG and Pattern Selection for Screening Small Delay Defects,” IEEE Int. Workshop on Current and Defect Based Testing (DBT’06), 2006.
  386. J. Plusquellic, D. Acharyya, A. Singh, M. Tehranipoor and C. Patel, “Multiple Supply Pad IDDQ_based Defect Detection Techniques Applied to Hardware Test Chips,” IEEE Int. Workshop on Current and Defect Based Testing (DBT’06), 2006.
  387. J. Plusquellic, D. Acharyya, A. Singh, M. Tehranipoor and C. Patel, “Triangulating to a Defect’s Physical Coordinates Using Multiple Supply Pad IDDQs: Test Chip Results,” in Proc. International Symposium for Testing and Failure Analysis Conference (ISTFA’06), 2006.
  388. N. Ahmed, M. Tehranipoor and V. Jayaram, “A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-Drop Effects,” in Proc. Int. Conf. on Computer-Aided Design (ICCAD’06), 2006.
  389. R. M. Rad and M. Tehranipoor, “A New Hybrid FPGA Using Nanoscale Cluster and CMOS Scale Routing,” in Proc. Design Automation Conference (DAC’06), 2006.
  390. N. Ahmed, M. Tehranipoor and V. Jayaram, “Timing-Based Delay Test for Screening Small Delay Defects,” in Proc. Design Automation Conference (DAC’06), 2006. Best Paper Candidate
  391. R. M. Rad and M. Tehranipoor, “A Reconfiguration-based Defect Tolerance Method for Nanosclae Devices,” in Proc. Int. Symposium on Defect and Fault Tolerance of VLSI Systems (DFT’06), 2006.
  392. R. M. Rad and M. Tehranipoor, “SCT: An Approach for Testing and Configuring Nanoscale Devices,” in Proc. IEEE VLSI Test Symposium (VTS’06), 2006.
  393. J. Lee, M. Tehranipoorand J. Plusquellic, “A Low-Cost Solution for Protecting IPs Against Side-Channel Scan-Based Attacks,” In Proc. IEEE VLSI Test Symposium (VTS’06), 2006.
  394. R. M. Rad and M. Tehranipoor, “Test Time and Defect Map Analysis of PLA and LUT-Based Nano-Architectures,” IEEE North Atlantic Test Workshop (NATW’06), 2006.
  395. N. Ahmed, M. Tehranipoor and V. Jayaram, “A Case Study of IR-Drop Effects During Faster-than-at-Speed Delay Test,” IEEE North Atlantic Test Workshop (NATW’06), 2006.
  396. J. Plusquellic, D. Acharyya, A. Singh, M. Tehranipoor and C. Patel, “Triangulating to a Defect’s Physical Coordinates Using Multiple Supply Pad IDDQs: Test Chip Results,” IEEE North Atlantic Test Workshop (NATW’06), 2006.
  397. J. Lee, N. Ahmed, M. Tehranipoor, V. Jayaram and J. Plusquellic, “A Novel Framework for Functionally Untestable Transition Fault Avoidance during ATPG,” IEEE North Atlantic Test Workshop (NATW’06), 2006.
  398. R. M. P. Rad and M. Tehranipoor, “Fine-Grained Island Style Architecture for Molecular Electronic Devices,” International Symposium on Field-Programmable Gate Arrays (FPGA’06) (Poster), 2006.
  399. M. Tehranipoor and R. M. P. Rad, “Test and Recovery for Fine-Grained Nanoscale Architectures,” International Symposium on Field-Programmable Gate Arrays (FPGA’06) (Poster), 2006.
  400. M. ElShoukry, C.P. Ravikumar and M. Tehranipoor, “Partial Gating Optimization for Power Reduction During Test Application,” in Proc. IEEE 14th Asian Test Symposium (ATS’05), 2005.
  401. M. Tehranipoor, M. Nourani and N. Ahmed, “Low Transition LFSR for BIST-Based Applications,” in Proc. IEEE 14th Asian Test Symposium (ATS’05), 2005.
  402. C.P. Ravikumar, N. Ahmed and M. Tehranipoor, “Practicing Transition-Fault Testing with Physical-Design-Friendly Flows,” Texas Instruments India Technical Conference (TIITC’05), 2005.
  403. J. Lee, M. Tehranipoor, C. Patel and J. Plusquellic, “Securing Scan Design Using Lock & Key Technique,” in Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05), 2005.
  404. N. Ahmed and M. Tehranipoor, “Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique,” in Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05), 2005.
  405. M. Tehranipoor, “Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure,” in Proc. International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’05), 2005.
  406. M. Alisafaee, S. M. Fakhraie and M. Tehranipoor, “Architecture of an Embedded Queue Management Engine for High-Speed Network Devices,” in Proc. IEEE MidWest Symposium on Circuits and Systems (MWSCAS’05), Cincinnati, 2005.
  407. H. Esmaeilzadeh, F. Farzan, N. Shahidi, S. M. Fakhraie, C. Lucas and M. Tehranipoor, “NnSP: Embedded Neural Networks Stream Processor,” in Proc. IEEE MidWest Symposium on Circuits and Systems (MWSCAS’05), 2005.
  408. N. Ahmed, M. Tehranipoor and C.P. Ravikumar, “Addressing At-speed Fault Coverage and Test Cost Issues Using Enhanced Launch-off-Capture,” Texas Instruments Symposium on Test (TIST’05), 2005.
  409. N. Ahmed, M. Tehranipoor and C.P. Ravikumar, “At-Speed Local Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers,” Texas Instruments Symposium on Test (TIST’05), 2005 (Ranked 5th Among 89 Presentations).
  410. N. Ahmed, M. Tehranipoor and C.P. Ravikumar, “Enhanced Launch-off-Capture Transition Fault Testing,” in Proc. IEEE International Test Conf. (ITC’05), 2005 (Received Top Ten Paper Recognition).
  411. N. Ahmed, M. Tehranipoor, C.P. Ravikumar and J. Plusquellic, “At-Speed Transition Fault Testing Using Low Speed Testers With Application to Reduced Scan Enable Routing Area,” IEEE North Atlantic Test Workshop (NATW’05), pp. 112-119, 2005.
  412. D. Acharyya, A. singh, M. Tehranipoor, C. Patel and J. Plusquellic, “Sensitivity Analysis of Quiescent Signal Analysis for Defect Detection,” IEEE. Int. Workshop on Defect Based Testing (DBT’05), pp. 3-10, 2005.
  413. M. Nourani, M. Tehranipoor and N. Ahmed, “Pattern Generation and Estimation for Power Supply Noise Analysis,” in proc. IEEE VLSI Test Symposium (VTS’05), pp. 439-444, 2005.
  414. N. Ahmed, C.P. Ravikumar, M. Tehranipoor and J. Plusquellic, “At-Speed Transition Fault Testing With Low Speed Scan Enable,” in proc. IEEE VLSI Test Symposium (VTS’05), pp. 42-47, 2005. Received Best Paper Award
  415. M. H. Tehranipour, M. Nourani and K. Chakrabarty, “Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression,” in proc. IEEE/ACM Design, Automation and Test in Europe (DATE’04), Paris, France, vol. 2, pp. 1284-1289, 2004.
  416. M. H. Tehranipour, M. Nourani, K. Arabi and A. Afzali-Kusha, “Mixed RL-Huffman Encoding for Power Reduction and Data Compression in Scan Test,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS’04), Vancouver, Canada, vol. 2, pp. 681-684, 2004.
  417. N. Ahmed, M. H. Tehranipour and M. Nourani, “Low-Power Pattern Generation for BIST Architecture,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS’04), Vancouver, Canada, vol. 2, pp. 689-692, 2004.
  418. N. Ahmed, M. H. Tehranipour, D. Zhou and M. Nourani,, “Frequency Driven Repeater Insertion for Deep Submicron,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS’04), Vancouver, Canada, vol. 5, 181-184, 2004.
  419. M. H. Tehranipour, N. Ahmed and M. Nourani, “Testing SoC Interconnects for Signal Integrity Using Boundary Scan,” in proc. IEEE VLSI Test Symposium (VTS’03), Napa, CA, pp. 158-163, 2003.
  420. N. Ahmed, M. H. Tehranipour and M. Nourani, “Extending JTAG for Testing Signal Integrity in SoCs,” in proc. IEEE/ACM Design, Automation and Test in Europe (DATE’03), Messe Munich, Germany, pp. 218-223, 2003.
  421. M. H. Tehranipour, N. Ahmed and M. Nourani, “Multiple Transition Model and Enhanced Boundary Scan Architecure to Test Interconnects for Signal Integrity,” in proc. IEEE International Conference on Computer Design (ICCD’03), San-Jose, pp. 554-559, CA, 2003.
  422. M. H. Tehranipour, M. Nourani and S. M. Fakhraie, “Systematic Test Program Generation for SoC Testing Using Embedded Processor,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS’03), Bangkok, Thailand, vol. 5, pp. 541-544, 2003.
  423. G. R. Chaji, R. M. Pourrrad, S. M. Fakhraie and M. H. Tehranipour, “eUTDSP: A Design Study of a New VLIW-Based DSP Architecture,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS’03), Bangkok, Thailand, vol. 4, pp. 137-140, 2003.
  424. M. H. Tehranipour and M. Nourani, “Signal Integrity Loss in SoC’s Interconnects: A Diagnostic Approach Using Embedded Microprocessor,” in proc. IEEE International Test Conference (ITC’02), Baltimore, MD, pp.1093-1102, 2002.
  425. S. M. Fakhraie, M. H. Tehranipour, M. R. Movahedin and M. Nourani, “Fast Prototyping of a DSP Core,” in proc. IEEE MidWest Symposium on Circuits and Systems (MWSCAS’02), Tulsa, Oklahoma, vol. 2, pp. 215-218, 2002.
  426. M. H. Tehranipour, M. Nourani, S. M. Fakhraie and C. A. Papachristou, “Test Optimization of Bus-Structured SoCs Using Embedded Microprocessor,” in proc. IEEE MidWest Symposium on Circuits and Systems (MWSCAS’02), Tulsa, Oklahoma, vol. 1, pp. 168-171, 2002.
  427. M. H. Tehranipour, Z. Navabi and S. M. Fakhraie, “An Efficient BIST for Embedded SRAM Testing,” in proc. IEEE International Symposium on Circuits And Systems (ISCAS’01), Sydney, Australia, Vol 5, pp. 73-76, 2001.
  428. M. H. Tehranipour, Z. Navabi and S. M. Fakhraie, “A Low-Cost BIST Architecture for Processor Cores,” in proc. IEEE Electronic Circuits and Systems Conference (ECS’01), Bratislava, Slovakia, pp. 11-14, 2001.
  429. M. H. Tehranipour and Z. Navabi, “Zero-Overhead BIST for Internal SRAM Testing,” in proc. IEEE International Conference on Microelectronics (ICM’00), Tehran, Iran, pp. 109-112, 2000.