Book Chapters

1. M. M. Hossain, F. Rahman, F. Farahmandi, and M. Tehranipoor, Firmware Protection, in Emerging Topics in Hardware Security, Springer, 2021.
2. M. M. Hossain, F. Rahman, F. Farahmandi, and M. Tehranipoor, Software Security with Hardware in Mind, in Emerging Topics in Hardware Security, Springer, 2021.
3. A. Nahiyan, M. He, Jungmin Park, and M. Tehranipoor, CAD for Side-Channel Assessment, in Emerging Topics in Hardware Security, Springer, 2021.
4. M. R. Makki, N. Pundir, M. Tehranipoor, and F. Farahmandi, Security Assessment of High-Level Synthesis, in Emerging Topics in Hardware Security, Springer, 2021.
5. P. Cui, U. Guin, and M. Tehranipoor, Trillion Sensors Security, in Emerging Topics in Hardware Security, Springer, 2021.
6. H. Wang, S. Chen, S. Islam Sami, F. Rahman, and M. Tehranipoor, Digital Twin with a Perspective from Manufacturing Industry, in Emerging Topics in Hardware Security, Springer, 2021.
7. M. Rahman and M. Tehranipoor, Blockchain-Enabled Electronics Supply Chain Assurance, in Emerging Topics in Hardware Security, Springer, 2021.
8. O. Arias, F. Rahman, M. Tehranipoor, and Yier Jin, “IoT Device Authentication: From a Cross-Layer Perspective,” 2020.
9. Q. Shi, D. Forte, and M. Tehranipoor, “Deterrent Approaches Against Hardware Trojan Insertion,” in Hardware Trojan War, Springer 2017.
10. S. Bhunia, A. Prasad Deb Nath, and M. Tehranipoor, “Introduction to Hardware Trojans,” in Hardware Trojan War, Springer 2017.
11. F. Rahman, A. Prasad Deb Nath, D. Forte, S. Bhunia, and M. Tehranipoor, “Nano CMOS Logic-Based Security Primitive,” in Security Opportunities in Nano Devices and Emerging Technologies, CRC Press, 2017.
12. H. Shen, F. Rahman, M. Tehranipoor, and D. Forte, “Carbon-Based Novel Devices for Hardware Security,” in Security Opportunities in Nano Devices and Emerging Technologies, CRC Press, 2017.
13. F. Rahman, A. Prasad Deb Nath, S. Bhunia, D. Forte, and M. Tehranipoor, “Composition of Physical Unclonable Functions: From Device to Architecture,” in Security Opportunities in Nano Devices and Emerging Technologies, CRC Press, 2017.
14. B. Shakya, X. Xu, N. Asadi, M. Tehranipoor, and D. Forte, “Leveraging Circuit Edit for Low-Volume Trusted Nanometer Fabrication,” in Security Opportunities in Nano Devices and Emerging Technologies, CRC Press, 2017.
15. U. Guin and M. Tehranipoor, and F. Forte, “Obfuscation and Encryption for Securing Semiconductor Supply Chain,” in Hardware Protection through Obfuscation, 2016.
16. Q. Shi, K. Xiao, D. Forte, and M. Tehranipoor, “Obfuscated Built-in Self Authentication,” in Hardware Protection through Obfuscation, 2016.
17. T. Rahman, D. Forte, M. Tehranipoor, “Protection of Assets from Scan Chain Vulnerabilities through Obfuscation,” in Hardware Protection through Obfuscation, 2016.
18. Z. Guo, M. Tehranipoor, and F. Forte, “Permutation based Obfuscation,” in Hardware Protection through Obfuscation, 2016.
19. B. Shakya, M. Tehranipoor, S. Bhunia, and F. Forte, “Introduction to Hardware Obfuscation: Motivation, Methods and Evaluation,” in Hardware Protection through Obfuscation, 2016.
20. Q. Shi, D. Forte and M. Tehranipoor, “Analyzing Circuit Layout to Probing Attack,” in Hardware IP Security and Trust: Validation and Test, 2016.
21. A. Nahiyan and M. Tehranipoor, “Code Coverage Analysis for IP Trust Verification,” in Hardware IP Security and Trust: Validation and Test, 2016.
22. H. Salmani and M. Tehranipoor, “Digital Circuits Vulnerability to Hardware Trojans,” in Hardware IP Security and Trust: Validation and Test, 2016.
23. A. Nahiyan, K. Xiao, D. Forte, and M. Tehranipoor, “Security Rule Check,” in Hardware IP Security and Trust: Validation and Test, 2016.
24. P. Mishra, S. Bhunia, and M. Tehranipoor, “Security and Trust Vulnerabilities in Third-Party IPs,” in Hardware IP Security and Trust: Validation and Test, 2016.
25. P. Mishra, S. Bhunia, and M. Tehranipoor, “The Future of Trustworthy Design,” in Hardware IP Security and Trust: Validation and Test, 2016.
26. K. Xiao, D. Forte, and M. Tehranipoor, “Circuit Timing Signature (CTS) for Detection of Counterfeit Integrated Circuits,” in Secure System Design and Trustable Computing, by Chip Hong Chang and Miodrag Potkonjak, 2015.
27. N. Tuzzio and M. Tehranipoor, “RSA: Implementation And Security,” in Introduction to Hardware Security and Trust, Springer, August 2011.
28. M. Tehranipoor and J. Lee, “Protecting IPs Against Scan-Based Side-Channel Attacks,” in Introduction to Hardware Security and Trust, Springer, August 2011.
29. J. Ma and M. Tehranipoor, “Introduction to VLSI Testing,” in Introduction to Hardware Security and Trust, Springer, August 2011.
30. M. Tehranipoor, “Built-In Self-Test and Defect Tolerance for Molecular Electronics-Based NanoFabrics,” in Robust Nano-Computing by Chao Huang, Springer 2010.
31. M. Tehranipoor and B. Sunar, “Hardware Trojan Horses,” in Towards Hardware Intrinsic Security: Foundation and Practice, by Ahmad R. Sadeghi, Springer, 2010.
32. M. Tehranipoor and N. Ahmed, “Faster-than-at-speed Test for Screening SDDs,” in Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits by Sandeep Goel and Krish Chakrabarty, Springer, 2010.
33. K. Peng, M. Yilmaz, and M. Tehranipoor, “Circuit Path-Grading Considering Layout, Process Variations, and Crosstalk,” in Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits by Sandeep Goel and Krish Chakrabarty, Springer, 2010.
34. M. Kassab amd M. Tehranipoor, “Test for Power Management Structures,” in Power Aware Testing and Test Strategies for Low Power Devices, by P. Girard, N. Nicolici, and X. Wen, Springer, 2009.
35. M. Tehranipoor, “Test and Defect Tolerance for Nanoscale Crossbar-based Circuits,” in System on Chip Test Architectures: Nanometer Design for Testability, by L.T. Wang, Charles Stroud and Nur Touba, Elsevier, Oct. 2007.
36. M. Tehranipoor and R. Rad, “Defect Tolerance for Reconfigurable Nanoscale Architectures,” in Emerging Nanotechnologies: Test, Defect Tolerance, and Reliability, by Mohammad Tehranipoor, Springer, 2007.